Intel Corporation

Esha Choukse

Suresh S Chittor

Vivek Joy Kozhikkottu

Shankar Ganesh Ramasubramanian

Melin Dadual

Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.

Techniques for setting a 2-level auto-close timer to access a memory device

In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

Growing community of inventors

Austin, TX, United States of America

Esha Choukse