Epcos Ag

Qualcomm Incorporated

Snaptrack Incorporated

Erwin Spits

Adrianus Van Bezooijen

Léon C M Van Den Oever

Francesco Gatta

Kevin Robert Boyle

Maurice Adrianus De Jongh

Hakan Inanoglu

David Loweth Winslow

Leon Metreaud

Robbin Damen

A user equipment (UE) is provided that detunes a receive antenna while a transmit antenna transmits. To determine the detuning, the UE first transmits a signal through the transmit antenna while the receive antenna is sequentially coupled through known loads. At each load, the UE determines an input reflection coefficient for a transmit path to the transmit antenna. Based upon the known loads and the corresponding input reflection coefficients, the UE determines a load to couple to the receive antenna to perform the detuning.

Computation-based detuning of coupled antennas

A user equipment (UE) is provided that includes an antenna switch array for demultiplexing a reference signal sequentially to each antenna in a plurality of antennas. While the antenna switch array selects an antenna, the UE measures a reflection coefficient for the antenna. The UE then tunes the antenna responsive to the reflection coefficient measurement.

Antenna impedance detection and tuning

A wireless communication device is provided with an in-device capability of characterizing the coupling between a pair of antennas. The wireless communication device determines the coupling through an operating gain measurement and through calibration gain measurements obtained through test ports.

In-device characterization of antenna coupling

An apparatus includes a radio-frequency (RF) path that includes an antenna tuner. The apparatus also includes calibration circuitry coupled to the antenna tuner. The calibration circuitry is configured to selectively isolate an antenna from a component of the RF path.

Calibration and adaptive control of antenna tuners

A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S_DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S_DR) into a first and second signal (S, S). The first signal (S) is associated to a first predetermined and the second signal (S) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA, PA). The first and second power amplifier stage (PA, PA) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA, PA) is operable to provide a first and second amplified signal (S_A, S), respectively, dependent on the first and second signal (S, S), respectively.

Power amplifier circuit and front end circuit

A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit.

Low-current logic plus driver circuit

A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.

Low-current logic-gate circuit

The circuit includes an E-mode transistor with gate-source junction, a D-mode transistor with gate-source junction, a component generating a voltage drop between the source of the D-mode transistor and the drain of the E-mode transistor, and a connection between the drain of the E-mode transistor and the gate of the D-mode transistor. The gate of the E-mode transistor is provided for an input signal, and the drain of the E-mode transistor is provided for an output signal.

Low-current inverter circuit

A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.

Low-current input buffer

A circuit includes a supply voltage and a control current line including two resistors. A sink current line branches off from the control current line between the resistors. A current sink transistor has an emitter that is connected to the sink current line and a collector that is connected to ground via a first further resistor. At least one reference transistor has an emitter that is connected to its base, to the supply voltage via a second further resistor and to the base of the current sink transistor. The collector of the reference transistor is connected to ground or to an emitter of a further reference transistor, which is switched in a manner similar to the first reference transistor.

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Utrecht, Netherlands

Erwin Spits