Siemens Aktiengesellschaft

Erwin P Jacobs

Ulrich Schwabe

Franz Neppl

Josef Winnerl

Gerhard Dorda

Dezso Takacs

Adolf Scheibe

Carlos-Alberto Mazure-Espejo

Dezsoe Takacs

A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by out-diffusion into the upper epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n.sup.+ /p.sup.+ spacing, and thus achieves a higher packing density with improved latch-up hardness.

Forming retrograde twin wells by outdiffusion of impurity ions in

A method for the simultaneous manufacture of bipolar and complementary MOS transistors on a common silicon substrate, wherein n-doped wells are produced in a p-doped substrate for accepting p-channel transistors and npn bipolar transistors are formed into the n-doped wells, the n-well forming the collector of the transistor and the n-wells overlying buried n.sup.+ -doped zones which are connected in the bipolar transistor region by more deeply extending collector plugs. A buried part and plug region of the collector are produced before the production of the wells, and the collector region is formed in the substrate in common with the well so the high-temperature step after the conventional LOCOS process is eliminated. The well implantation is self-adjusting relative to the implantation of the deep collector plug which is annularly formed in the well. A reduction of the collector series resistance as well as an increased latch-up hardness is obtained. Further, the parasitic substrate-pnp is reduced. The method is particularly useful for the manufacture of VLSI circuits with high switching speeds.

Method for the simultaneous manufacture of bipolar and complementary MOS

A method for the manufacture of a large scale integration (LSI) MOS field effect transistor wherein a gate electrode is generated on a doped silicon substrate, source/drain regions are formed by ion implantation using the gate electrode as an implantation mask and the source/drain regions are shielded by means of an oxide layer extending to the sidewalls of the gate electrode so that the diffusion of the implanted source/drain regions under the gate electrode area are reduced. The specific improvement of the present invention involves applying a readily flowable silicate glass layer as a gate edge masking for the source/drain ion implantation after formation of the gate electrode, the silicate glass layer being applied by deposition from the vapor phase at a thickness such that the dopant ions in the subsequent source/drain ion implantation are still implanted into the zone near the surface under the silicate glass layer but ion implantation into the zones at the edges of the gate is suppressed.

Method of making MOS FETs using silicate glass layer as gate edge

A method for manufacturing a CMOS circuit wherein a process sequence matched to an n-tub manufacture is carried out. Short-channel properties of n-channel transistors are improved by performing double boron implantations of the channel regions. A single channel implantation is executed for both transistor types. Compared to traditional CMOS processes in n-tub structure, this eliminates involved masking steps. Also, the polysilicon gate is shielded from the boron ion implantation by means of a masking re-oxidation step and the under-diffusion given n-channel and p-channel transistors is greatly reduced by means of pull-back of the boron source/drain implantation. This contributes significantly to a symmetrical U.sub.T behavior of the transistors and to the attainment of high switching speeds. The method is used in the manufacture of VLSI CMOS circuits in VLSI technology.

Method of making CMOS circuits by twin tub process and multiple

A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits). By use of a suitable gate material, preferably a gate material comprised of silicides of high melting point metals, a threshold voltage of n-channel and p-channel CMOS-FETs having gate oxide thicknesses d.sub.GOX in a range of 10 to 30 nm is simultaneously symmetrically set by means of a single channel ion implantation. Given employment of tantalum silicide, the gate oxide thickness d.sub.GOX is set to 20 nm and the channel implantation is executed with a boron dosage of 3.times.10.sup.11 cm.sup.-2 and an energy of 25 keV. In addition to achieving a high low-level break down voltage for short channel lengths, this enables the elimination of a photolithographic mask. This represents an improvement with respect to yield and costs. The method serves for the manufacture of analog and digital CMOS circuits in VLSI technology.

Method for manufacturing VLSI complementary MOS field effect circuits

A memory cell comprises a double gate field effect transistor which exhibits source and drain regions located in a semiconductor body and two gate electrodes covering the semiconductor area between the source and drain regions, the gate electrodes being separated from the semiconductor body by a multilayer insulation. The first gate electrode is a memory gate, whereas inversion layers are produced with the second gate electrode given supply of a gate voltage, the inversion layers extending the source and drain regions in the direction towards the memory gate. The structure provides a surface-saving design of a selection element. The second gate electrode is employed for this purpose as the selection element and is connected to a selection line (word line). The invention finds application in very large scale integrated semiconductor memories.

Memory cell having a double gate field effect transistor and a method

Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d.sub.6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d.sub.4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, d.sub.cox, of the capacitor structures (5b, 12). This technique is useful for manufacturing VLSI CMOS circuits in VLSI technology with and without switched capacitors.

Method for manufacturing VLSI complementary MOS field effect transistor

Analog or digital MOS circuits in VLSI technology are produced by a method in which the manufacture of two troughs (5, 8) occurs with only one mask (3) used in production of the p-trough (5). The n-trough (8) is formed by a surface-wide implantation (7) of an ion selected from a group consisting of P, As and Sb. The channel implantation of the p-transistors occurs simultaneously. The field (11) and channel (12) implantation of the n-channel transistors is carried out with a silicon nitride mask (9), i.e., a LOCOS mask, and a double boron implantation (10a, 10b). The field implantation (16) of the p-channel transistors is carried out with arsenic (15). Advantages of this process sequence include reduction of parasistic edge capacitances at the source/drain edges with fewer masking steps.

Method for producing VLSI complementary MOS field effect transistor

The invention provides a method for manufacturing adjacent tubs implanted with dopant material ions in the manufacture of LSI complementary MOS field effect transistor circuits (CMOS circuits), and also provides a method sequence for a CMOS process adapted to tub manufacture. In accordance with the principles of the invention, for the greatest possible spatial separation of the tubs, a p-tub (5) is produced before a n-tub (8) and an undercutting (25) of a nitride layer (4) serving as the implantation mask in the p-tub production is intentionally produced, so that, during a subsequent oxidation, the edge of the oxidation is shifted toward the outside by about 1 to 2 .mu.m. Further, the penetration depth x.sub.jn of the n-tub (8) is set smaller by a factor at least equal to 4 relative to the penetration depth x.sub.jp of the p-tub (5), whereby the thickness of the n-doped epitaxial layer (2) and the penetration depth x.sub.jp are about matched to one another. The two tubs are separately implanted and diffused. As a result of the inventive sequences, the disadvantages of mutual, extensive compensation of the p-tub and the n-tub are avoided.

Process for producing adjacent tubs implanted with dopant ions in the

A method for manufacturing MNOS memory transistors with very short channel lengths in silicon gate technology. In a substrate of a first semiconductor type, source and drain zones of MNOS and MOS components of a second conductivity type opposite the first conductivity type are provided. The edges of gate electrodes, with reference to the plane of the substrate surface, lie perpendicularly and self-adjusting over the edges of the source and drain zones, whereby the source and drain zones generated in the substrate are manufactured by means of ion implantation upon employment of the gate electrodes as the implantation mask.

Method of making very short channel length MNOS and MOS devices by

The invention relates to a MNOS memory cell arrangement in VLSI (very large scale integration) technology comprised of a multi-layer gate insulating layer covering a surface of a semiconductor body in the region between the source and drain zones. In order to avoid breakdowns at the source and drain zone edges before an erasure voltage is attained, the gate electrode is split into two electrodes, which can be operated in different ways and which are superimposed on upon another. These gate electrodes are connected via self-aligned, overlapped contacts. This arrangement resolves 'short channel erasure', even in the case of VLSI technology. The invention can be applied as required to MNOS EEPROM memory devices.

MNOS Memory cell

Integrated MOS circuits with and without MNOS memory transistors in silicon-gate technology are produced with overlapped contacts using a silicon nitride mask. After production of structured SiO.sub.2 layers on a p- or n- doped semiconductor substrate to separate active transistor zones in accordance with the so-called LOCOS process, a silicon nitride layer is deposited onto the surface and is then structured so that the zones in which a gate oxide is to be produced, are uncovered and during gate oxidation, the surface of this structured silicon nitride layer is converted into an oxynitride layer. In contrast to previously known processes, the invention provides self-aligned overlapped contacts with oversized contact holes. The silicon-nitride layer functions as an etch-stop during etching of an intermediate oxide. This avoids under-etching of the polysilicon during contact hole etching. The overlapped contacts allow a substantial increase in the packing and integration density of the so-produced circuits.

Process for production of integrated MOS circuits with and without MNOS

An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a 'blocking' layer. The 'blocking' layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO.sub.2 layer and has a layer thickness of about 5 to 30 nm. Such 'blocking' layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.

Process for producing an integrated multi-layer insulator memory cell

A static storage element in a field effect transistor arrangement, has source and drain zones in a semiconductor body and a gate insulation layer provided on the surface of the semiconductor body. A spatial region having a high lattice defect or trap density is formed in the gate insulation layer for storing a quantity of charge which can be altered by electromagnetic radiation.

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Vaterstetten, Germany

Erwin P Jacobs