Nxp B.v.

Koninklijke Philips Corporation N.V.

Integrated Device Technology, Inc.

Erwin Janssen

Konstantinos Doris

Athon Zanikopoulos

Cicero Silveira Vaucher

Yu Lin

Vladislav Dyachenko

Gerrit Willem Den Besten

Derk Reefman

Frank Leong

Johannes Hubertus Antonius Brekelmans

Ewout Brandsma

Dolphin Abessolo Bidzo

Hendrik Van Der Ploeg

Johannes H A Brekelmans

Sander Derksen

Erwin Johannes Gerardus Janssen

Antonius De Graauw

Klaas De Waal

Anton Zanikopoulos

Alessandro Murroni

Claudio Nani

Bernardus Johannes Martinus Kup

An electro-static discharge (ESD) protection system for a wireless transceiver comprises a switch circuit at a first terminal and a second terminal of a low noise amplifier; a primary ESD protection circuit between an input terminal and a low voltage supply terminal of the wireless transceiver for shunting a first source of current of an ESD event; a clamp element between a high voltage supply terminal and the low voltage supply terminal having a clamping voltage that is less than a breakdown voltage of the LNA for preventing a second source of current of the ESD event from receipt by the LNA; and a power supply ESD clamp element between the high voltage supply terminal and the low voltage supply terminal for shunting a third source of current of the ESD event at the high voltage supply terminal.

Electrostatic discharge protection for wireless device

A successive approximation register, SAR, analog-to-digital converter, ADC, () is described. The SAR ADC () includes: a track and hold circuit () configured to sample an analog input signal (); a comparator () coupled to the track and hold circuit and configured to compare the sampled analog input signal () with a DAC () output voltage; and a feedback path () that comprises a digital-to-analog converter, DAC, () configured to generate the reference voltage that approximates the input analog signal (). The SAR ADC () further includes a dither circuit () coupled to or located in the feedback path () and arranged to add a dither signal at an input of the DAC () in a first time period and subtract the dither signal from the output digital signal routed via the feedback path () and input of the DAC () in a second time period during a conversion phase of the SAR ADC ().

Successive approximation register (SAR) analog-to-digital converter (ADC), radar unit and method for improving harmonic distortion performance

A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component.

Method and apparatus for generating a frequency estimation signal

A front end for a radar system and method of operation are described. A timing circuit controls operation of a transmitter circuit and a receiver circuit and outputs a valid data signal indicating whether the receiver circuit will be receiving a reflected radar signal. A converter converts a received radar signal and outputs digital data. A serialising circuit receives the digital data and supplies a serial data stream including the digital data for a data processing device. The valid data signal is also communicated to the converter to cause the converter to output a bit pattern corresponding to a code word when the valid data signals indicates that the receiver circuit will not be receiving the reflected radar signal and to output a bit pattern corresponding to a data word including radar data when the valid data signals indicates that the receiver circuit will be receiving the reflected radar signal.

Front end for a radar system and method of operation a front end for a radar system

Receivers and methods of testing are described. A receiver includes a plurality of receiver channels, each including an amplifier for receiving a signal from an antenna and a mixer downstream of the amplifier. A test signal generating circuit is configured to generate test signals. A signal path connects the test signal generating circuit and each receiver channel and couples to each receiver channel at a coupling between the amplifier and a mixer. A test signal from the test signal generating circuit is injectable to the parts of the receiver channel downstream of the amplifier. The test signal may alternatively be injected into the entire receiver channel. The receivers and methods may be used in wireless systems, such as radar systems and radio systems.

Receiver testing

There is disclosed an apparatus comprising a first phase-locked loop comprising: a phase detector (), arranged to receive a reference clock signal () and a feedback clock signal () and to output a frequency control signal based on a phase difference between the reference clock signal () and the feedback clock signal (); a variable-frequency oscillator () arranged to output an oscillator signal having a frequency dependent on said frequency control signal; first divider circuitry () for generating said feedback clock signal () by frequency-dividing said oscillator signal; and second divider circuitry () for generating an output clock signal (by frequency-dividing said oscillator signal; wherein a phase relation between said first divider circuitry () and said second divider circuitry () is adjustable to delay or advance said output clock signal () relative to said feedback clock signal (). The apparatus may be a radar receiver or transceiver.

Apparatus comprising a phase-locked loop

A successive approximation register, SAR, analog-to-digital converter, ADC, () is described. The SAR ADC () includes: an analog input signal (); an ADC core () configured to receive the analog input signal () and comprising: a digital to analog converter, DAC () located in a feedback path; and a SAR controller () configured to control an operation of the DAC (), wherein the DAC () comprises a number of DAC cells, arranged to convert a digital code from the SAR controller () to an analog form; a digital signal reconstruction circuit () configured to convert the digital codes from the SAR controller () to a binary form; and an output coupled to the digital signal reconstruction circuit () and configured to provide a digital data output (). The DAC () is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller () is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC () and the digital signal reconstruction circuit () to implement a small signal mapping mode of operation.

Successive approximation register analog-to-digital converter, electronic device and method therefor

An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.

Analog-to-digital converter

A data conversion system and method are described. A first phase locked loop includes a controllable frequency oscillator circuit to receive a digital data stream and output a reference frequency signal, and includes an oscillator and at least one variable load connected to the oscillator which is controllable to tune the oscillator frequency and vary the frequency of the reference frequency signal. A second phase locked loop includes a divide by N function in a feedback loop (where N has an integer value), and receives the reference frequency signal and outputs a recovered clock signal corresponding to an original clock signal associated with the digital data stream. The recovered clock signal is used to clock a data converter to convert the digital data into an analog output signal.

Data conversion

A method of performing a service scan for available channels across a bandwidth of an input signal, the method comprising the steps of: acquiring a power spectrum of the input signal bandwidth; analyzing the power spectrum to identify a list of candidate channels, each candidate channel being identified by at least a center frequency; processing each of the candidate channels in a receiver unit to extract service information, if present, relating to the candidate channel; and storing the service information for the channel in a memory.

Fast service scan

Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase.

Track and hold circuit using a bootstrapping circuit

A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.

Successive approximation register ADC circuits and methods

A digital signal processing circuit comprises a band selector () for selecting at least one sub-band from a frequency spectrum of a digital sampled input signal. The band selector () comprises a plurality of processing branches corresponding to respective phases and an adder () for adding branch signals from the branches. Each branch comprises a sub-sampler () for sub-sampling sample values of the input signal at the phase corresponding to the branch, a filter () with a first FIR filter (), applied alternatingly to sets of even and to sets of odd samples from the subsampler () and a second FIR filter () applied to further sets of odd and even samples from the subsampler () when the first FIR filter is applied to the even and odd sets respectively. Output samples from the first and second FIR filter () are combined to form the branch signals of the branch, according to a changing combination pattern that changes cyclically as a function of sample position and depends on a phase for which the branch is used.

Digital signal processing circuit and method comprising band selection

This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit. In another embodiment the DAC signal is routed through a separate second buffer circuit. By use of a single buffer circuit, or where there is ideal matching of the buffer circuits in the latter embodiment, the distortion effects are completely eliminated; however, for practical imperfectly matched buffer circuits according to the latter embodiment, the gain and off-set mismatches can be accommodated through calibration of the buffers or, in suitable applications, through the DAC calibration.

The invention relates to a circuit and method for receiving a signal of which&#x2014;at the receiver end&#x2014;the frequency is basically unknown. By sampling the data and deriving the frequency of the signal (or actually: the data rate of the data carried by the signal) and setting a phase locked loop in the receiver to the derived&#x2014;estimated&#x2014;circuit, the receiver can very quickly tune in to the frequency of the signal. Hence, no embedded or accompanying clock is required for the signal. Oversampling of the signal by the receiver front end is preferred, though.

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Veldhoven, Netherlands

Erwin Janssen