Freescale Semiconductor,inc.

Motorola Corporation

Erwin J Prinz

Craig T Swift

Robert F Steimle

Frank Kelsey Baker, Jr

Ko-Min Chang

Ramachandran Muralidhar

Michael Alan Sadd

Gowrishankar L Chindalore

Alexander Hoefler

Rajesh A Rao

Jane A Yater

Bruce E White

Kuo-Tung Chang

Paul A Ingersoll

Mehul D Shroff

Bruce L Morton

Wayne M Paulson

Peter J Kuhn

Wei-Ming Chen

Kevin Yun-kang Wu

Mohammed Suhail

Sung-Wei Lin

Gregory M Yeric

Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.

Method for simulating long-term performance of a non-volatile memory by exposing the non-volatile memory to heavy-ion radiation

A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Split gate memory cell and method therefor

A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.

Silicided nonvolatile memory and method of making same

A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate () is provided, and first and second sets of memory stacks (, and) are formed on the substrate, each memory stack including a control gate () and a layer of memory material (). A source/drain region () is then formed between the first and second sets of memory stacks, and a silicide layer () is formed over the source/drain region.

Nanocrystal bitcell process integration for high density application

A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.

Method for process integration of non-volatile memory cell transistors with transistors of another type

A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types

A method for forming a semiconductor device includes forming a first gate electrode over a semiconductor substrate, wherein the first gate electrode comprises silicon and forming a second gate electrode over the semiconductor substrate and adjacent the first gate electrode, wherein the second gate electrode comprises silicon. Nanoclusters are present in the first gate electrode. A peripheral transistor area is formed devoid of nanoclusters.

Method for forming a non-volatile memory and a peripheral device on a semiconductor substrate

A split gate memory cell can include a first gate electrode and a second gate electrode. The split gate memory cell can also include a first diffusion region underlying a trench in a semiconductor substrate, wherein the trench has a sidewall, and the first diffusion region lies closer to the first gate electrode than the second gate electrode. The split gate memory cell can further include a second diffusion region lying outside the trench, wherein the second diffusion region lies closer to the second gate electrode than the first gate electrode. The split gate memory cell can still further include a charge storage layer adjacent to the sidewall of the trench, wherein the charge storage layer includes discontinuous storage elements. Methods of forming and using the split gate memory cell are also disclosed.

Split gate storage device including a horizontal first gate and a vertical second gate in a trench

In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Method of discharging a semiconductor device

A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

Semiconductor device with nanoclusters

A non volatile memory includes a plurality of transistors having a non conductive storage medium. The transistors are erased by injecting holes into the storage medium from both the source edge region and drain edge region of the transistor. In one example, the storage medium is made from silicon nitride isolated from the underlying substrate and overlying gate by silicon dioxide. The injection of holes in the storage medium generates two hole distributions having overlapping portions. The combined distribution of the overlapping portions is above at least a level of the highest concentration of program charge in the overlap region of the storage medium. In one example, the transistors are programmed by hot carrier injection. In some examples, the sources of groups of transistors of the memory are decoded.

Erase of a memory having a non-conductive storage medium

A non volatile memory () includes an array () of transistors () having discrete charge storage elements (). The transistors are programmed by using a two step programming method () where a first step () is hot carrier injection (HCl) programming with low gate voltages. A second step () is selectively utilized on some memory cells to modify the injected charge distribution to enhance the separation of charge distribution between each memory bit within the transistor memory cell. The second step of programming is implemented without adding significant additional time to the programming operation. In one example, the first step injects electrons and the second step injects holes. The resulting distribution of the two steps removes electron charge in the central region of the storage medium.

Programming of a memory with discrete charge storage elements

A semiconductor nonvolatile memory cell ( ) comprising a split-gate FET device having a charge-storage transistor ( ) in series with a select transistor ( ). A multilayered charge-storage gate dielectric ( ) extends over at least a portion of the source ( ) and a first portion ( ) of the channel of the FET. A select gate dielectric ( ), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain ( ) and a second portion ( ) of the channel. A monolithic gate conductor ( ) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer ( ). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Split-gate thin-film storage NVM cell

A method of discharging a charge storage location of a transistor of a non-volatile memory includes applying first and second voltages to a control gate and a well region, respectively, of the transistor. The first voltage is applied to the control gate of the transistor, wherein the control gate has at least a portion located adjacent to a select gate of the transistor. The transistor includes a charge storage location having nanoclusters disposed within dielectric material of a structure of the transistor located below the control gate. Lastly, a second voltage is applied to the well region located below the control gate. Applying the first voltage and the second voltage generates a voltage differential across the structure for discharging electrons from the nanoclusters of the charge storage location.

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Austin, TX, United States of America

Erwin J Prinz