Nxp B.v.

Koninklijke Philips Corporation N.V.

Nexperia B.v.

Interuniversitair Micro-elektronica Centrum Vzw

Erwin Hijzen

Raymond J E Hueting

Philippe Meunier-Beillard

Michael A A In'T Zandt

Johannes J T M Donkers

Anco Heringa

Michael A A In 't Zandt

Roel Daamen

Jan Sonsky

Radu Surdeanu

Abraham Rudolf Balkenende

Wibo Daniel Van Noort

Prabhat Agarwal

Godefridus Adrianus Maria Hurkx

Johannes Donkers

Sebastien Nuttinck

Joost Melai

Liang Yan

Johannes Josephus Theodorus Marinus Donkers

Petrus Hubertus Cornelis Magnee

Rob Van Dalen

Andreas Hubertus Montree

Gerhard Koops

Erik Petrus Antonius Maria Bakkers

Francois Neuilly

Stefaan Van Huylenbroeck

Christelle Rochefort

Jurriaan Schmitz

Mark A Gajda

Gerrit E J Koops

Raymond Josephus Engelbart Hueting

Erik P A M Bakkers

Magali Lambert

Andreas M Piontek

Michael Zandt

Philippe Meunier-Bellard

Guillaume L R Boccardi

Li Jen Choi

Raymond Josephus Hueting

Michael A A Zand In't

Melanie Maria Hubertina Wagemans

Giberto Curatola

A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor.

Semiconductor device having control conductors

An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Semiconductor device with an integrated heat sink array

Semiconductor device with heat sinks

A method of manufacturing a structure (), the method comprising forming a cap element () on a substrate (), removing material () of the substrate () below the cap element () to thereby form a gap () between the cap element () and the substrate (), and rearranging material of the cap element () and/or of the substrate () to thereby merge the cap element () and the substrate () to bridge the gap ().

Sealing structure and method of manufacturing the same

A semiconductor device () comprising a bipolar transistor and a fieldeffect transistor within a semiconductor body () comprising a projecting mesa () within which are at least a portion of a collector region (and) and a base region () of the bipolar transistor. The bipolar transistor is provided with an insulating cavity () provided in the collector region (and). The insulating cavity () may be provided by providing a layer () in the collector region (), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer () to provide the cavity using the access path. The layer () provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity () provides a reduction in the base collector capacitance and can be described as defining the base contact.

Semiconductor device and method of manufacture thereof

Disclosed is an integrated circuit () comprising a substrate () carrying a plurality of light-sensitive elements () and a blazed grating () comprising a plurality of diffractive elements () for diffracting respective spectral components (-) of incident light () to respective light-sensitive elements (), the blazed grating () comprising a stack of layers, at least some of these layers comprising first portions, e.g. metal portions () arranged such that each diffractive element () comprises a stepped profile of stacked first portions with a first portion in a higher layer laterally extending beyond a first portion in a lower layer of said stepped profile.

Integrated circuit with grating and manufacturing method therefor

Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (), a layer () of semiconductor material, a first insulating layer (), and a second insulating layer () which is selectively etchable with respect to the first insulating layer. A trench () is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion () therethrough. A window () is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

Method of manufacturing a bipolar transistor semiconductor device and semiconductor devices obtained thereby

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () comprising a bipolar transistor with in that order a collector region (), a base region (), and an emitter region (), wherein the semiconductor body comprises a projecting mesa () comprising at least a portion of the collector region () and the base region (), which mesa is surrounded by an isolation region (). According to the invention, the semiconductor device () also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (), and a gate region (), which gate region () forms a highest part of the field effect transistor, and the height of the mesa () is greater than the height of the gate region (). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Semiconductor device and method of manufacturing such a device

The invention relates to a method of manufacturing a semiconductor device () with a substrate () and a semiconductor body () which is provided with at least one bipolar transistor having an emitter region (), a base region () and a collector region (), wherein in the semiconductor body () a first semiconductor region () is formed that forms one () of the collector and emitter regions () and on the surface of the semiconductor body () a stack of layers is formed comprising a first insulating layer (), a polycrystalline semiconductor layer () and a second insulating layer () in which stack an opening () is formed, after which by non-selective epitaxial growth a further semiconductor layer () is deposited of which a monocrystalline horizontal part on the bottom of the opening () forms the base region () and of which a polycrystalline vertical part (A) on a side face of the opening () is connected to the polycrystalline semiconductor layer (), after which spacers (S) are formed parallel to the side face of the opening () and a second semiconductor region () is formed between said spacers (S) forming the other one () of the emitter and collector regions (). According to the invention the above method is characterized in that before the further semiconductor layer () is deposited, the second insulating layer () is provided with an end portion (A) that viewed in projection overhangs an end portion (A) of the underlying semiconductor layer (). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.

Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

The invention relates to a method according to the part of the surface of the semiconductor body adjoining the opening and which is to be kept free is provided with a cover layer after which the high-crystalline layer is formed by means of a deposition process. The material of the cover layer can then easily be chosen such that it can be selectively etched relative to the silicon underneath. In addition, the cover layer can easily be selectively deposited on the relevant part of the surface because use can be made of an anisotropic deposition process. In such a process the cover layer is not deposited in the hollow and on the bottom of the hollow. It will be apparent that for the high-crystalline layer also other materials can be chosen such as SiGe having such low Ge contents that the SiGe cannot be etched selectively very well compared to the Silicon.

Method of manufacturing a bipolar transistor and bipolar transistor obtained therewith

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region () of a metallic material that is connected to a conductive region () of a metallic material sunken from the surface of the semiconductor body (), by which the buried conductive region () is made electrically connectable at the surface of the semiconductor body (). According to the invention, the buried conducting region () is made at the location of the active region (A) of the semiconductor body (). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.

Semiconductor device with low buried resistance and method of manufacturing such a device

A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region () is formed and patterned, base contact regions () formed on either side, and a gap formed between the base contact region. A base (), spacers () and an emitter () are formed in the gap.

Method of making bipolar transistor

The invention relates to a semiconductor device () with a semiconductor body () comprising a bipolar transistor with an emitter region, a base region and a collector region () of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions () comprises a nanowire (). The base region () has been formed from a layer () at the surface of the semiconductor body (); the other one () of the emitter or collector regions () has been formed in the semiconductor body () below the base region (). The emitter or collector region () comprising the nanowire () has been provided on the surface of the semiconductor body () such that its longitudinal axis extends perpendicularly to the surface.

Semiconductor device and method of manufacturing the same

The invention relates to a method of manufacturing a semiconductor device comprising a field effect transistor, in which method a semiconductor body of silicon with a substrate is provided at a surface thereof with a source region and a drain region of a first conductivity type which are situated above a buried isolation region and with a channel region, between the source and drain regions, of a second conductivity type, opposite to the first conductivity type, and with a gate region separated from the surface of the semiconductor body by a gate dielectric and situated above the channel region, wherein a mesa is formed in the semiconductor body in which the channel region is formed and wherein the source and drain regions are formed on both sides of the mesa in a semiconductor region that is formed using epitaxial growth, the source and drain regions thereby contacting the channel region.

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () comprising a vertical bipolar transistor with an emitter region, a base region and a collector region () of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region () comprises a first sub-region (A) bordering the base region () and a second sub-region (B) bordering the first sub-region (A) which has a lower doping concentration than the second sub-region (B), and the transistor is provided with a gate electrode () which laterally borders the first sub-region (A) and by means of which the first sub-region (A) may be depleted. According to the invention the collector region () borders the surface of the semiconductor body (), while the emitter region () is recessed in the semiconductor body (), and the collector region () forms part of a mesa structure () formed at the surface of the semiconductor body (). Such a device () has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector () comprises a nanowire () forming the mesa structure ().

Growing community of inventors

Blanden, Belgium

Erwin Hijzen