International Business Machines Corporation

Erwin F Pfeffer

Lisa Cranton Heller

Timothy John Slegel

Dan F Greiner

Damian Leo Osisek

Charles Franklin Webb

Ute Gaertner

Charles W Gainey, Jr

Kenneth E Plambeck

Gustav E Sittmann, Iii

Timothy J Siegel

Bruce A Wagar

Hans-Werner Tast

Norbert Hagspiel

Klaus J Getzlaff

Chung-Lung K Shum

Donald W Schmidt

Leslie W Wyman

Jaya Srikrishnan

Jane Helen Bartik

Kerstin Claudia Schelm

Heinz Baier

Martin Schneiderhan

Frank Siegfried Lehnert

Wilhelm Ernst Haller

Juergen Haess

Barry Watson Krumm

Michael Klaus Kroener

Thomas G Koehler

Joerg Deutschle

Guenter Gerwig

Matthias Fertig

Michael H Kallmeyer

Charles E Webb

Gunter Gerwig

Thomas Pfluger

Hans-Peter Reimann

John D MacDougall

Klaus J&ouml;rg Getzlaff

Oliver Laub

Peter Loffler

Klaus-Joerg Getzlaff

Peter Koepp

Debbie A St Onge

Hans Rosch

Peter Kopp

An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

Creating a dynamic address translation with translation exception qualifiers

What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

Dynamic address translation with access control in an emulator environment

What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.

Dynamic address translation with fetch protection in an emulated environment

An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Invalidating a range of two or more translation table entries and instruction therefor

Invalidating a range of two or more translation table entries and instruction therefore

An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

Dynamic address translation with translation table entry format control for identifying format of the translation table entry

Creating a dynamic address translation with translation exception qualifier

A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.

Emulation of a dynamic address translation with change record override on a machine of another architecture

What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

Load page table entry address instruction execution based on an address translation format control field

Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined whether the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations managed in different zones of memory. Based on determining that the memory address refers to the SMO, it is determined whether the configuration has access to the SMO. Based on determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the configuration and the plurality of configurations is allowed.

Shared memory translation facility

Growing community of inventors

Wuerttemberg, Germany

Erwin F Pfeffer