Micron Technology Incorporated

Intel Corporation

Ervin T Hill

Zengtao T Liu

Hongmei Wang

Amitava Majumdar

Shawn D Lyonsmith

Rajesh Kamana

Marlon W Hug

Krishna Kumar Parat

Pranav Kalavade

Kiran Pangal

Bhumika Chhabra

Anish A Khandekar

Farrell Martin Good

Oleh Karpenko

Robert K Grubbs

Kevin Lee Baker

Linda N Marquez

Henry Chao

Jay Steven Brown

Jixin Yu

Gordon T McGarvey

Jeffrey B Hull

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.

Dielectric barrier at non-volatile memory tile edge

Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

Non-contact measurement of memory cell threshold voltage

Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Non-contact electron beam probing techniques and related structures

Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.

Apparatus and methods for improved flash cell characteristics

A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular temperature to form an undoped polysilicon. The method also includes depositing a second precursor material on a surface of the undoped polysilicon at substantially the same temperature, wherein the undoped polysilicon serves as a seed to accelerate forming a doped polysilicon.

Methods of semiconductor processing involving forming doped polysilicon on undoped polysilicon

A method of forming high performance logic transistors and high density flash transistors on a single substrate is disclosed. In one embodiment, the method comprises: forming a logic gate stack in a logic region on a substrate, forming a flash memory gate stack in a flash region on the substrate, depositing a hardmask layer over the logic gate stack and over the flash memory gate stack, patterning the hardmask in the logic region so that areas of hardmask remain where logic gates are desired, patterning the flash gate stack in the flash region to form flash memory gates, and etching the logic gate stack using the remaining hardmask as a mask to form logic gates.

Method for manufacturing high density flash memory and high performance logic on a single die

A method of forming a thin film stack on a substrate, wherein the thin film stack includes at least a polysilicon layer and an oxide layer; forming a hardmask layer on the thin film stack; forming an anti-reflective coating (ARC) layer on the hardmask layer; patterning the ARC layer; etching the hardmask layer using the patterned ARC layer as a mask; and etching the thin film stack using the hardmask layer as a mask.

Method and apparatus for self-aligned MOS patterning

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Boise, ID, United States of America

Ervin T Hill