Freescale Semiconductor,inc.

Nxp USA, Inc.

Ertugrul Demircan

Mehul D Shroff

Jack M Higman

Edward Outlaw Travis, Jr

Douglas Michael Reber

Thomas F McNelly

Kenneth J Danti

Michael A Stockinger

Yang Du

Dwarka Prasad

Donald E Smeltzer

Inder Mohan Bhawnani

A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.

Method for verifying design rule checks

This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are 'pre-marked' and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.

Integrated circuit design using pre-marked circuit element object library

A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.

Techniques for electromigration stress mitigation in interconnects of an integrated circuit design

A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.

Inductive element with interrupter region and method for forming

An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.

Prioritized design for manufacturing virtualization with design rule checking filtering

In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment.

Techniques for electromigration stress determination in interconnects of an integrated circuit

Inductive element with interrupter region

A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.

Method and system for physical verification using network segment current

A technique for determining stress in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph. The directed graph represents an interconnect of an integrated circuit design. The technique also includes locating a first point on the spanning tree that has a lowest stress and a second point on the spanning tree that has a highest stress. The technique further includes determining whether a maximum first stress between the first and second points is less than a critical stress.

An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.

Integrated circuits with edge-adjacent devices having reactance values

Semiconductor device with capacitor and/or inductor and method of making

A method for forming an integrated circuit () comprises accessing () a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code of at least one previously placed primitive cell () of the integrated circuit layout is used. A primitive cell is selected () from the library that is compatible with the at least one previously placed primitive cell and the selected primitive cell is placed into the integrated circuit layout adjacent the at least one previously placed primitive cell. The integrated circuit is manufactured () using the integrated circuit layout.

Primitive cell method for front end physical design

An integrated circuit capacitor ( ) uses multiple electrically conductive stacks ( ) to optimize capacitance density. A second stack ( ) is a first nearest neighbor to a first stack ( ). A third stack ( ) is a second nearest neighbor to the first stack. Each of the three stacks defines vertices of an isosceles triangle ( ) formed in a plane substantially perpendicular to the three stacks. The isosceles triangle does not have a ninety degree angle. The isosceles triangle may also be implemented as an equilateral triangle.

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Austin, TX, United States of America

Ertugrul Demircan