Alcatel Network Systems, Inc.

Alcatel Na, Inc.,

Timothy James Williams

Ertugrul Baydar

Timothy J Williams

William B Weeber

Richard Marion Czerwiec

Joseph E Sutherland

Joseph Lee Smith

William E Powell

Michael J Gingell

Claude M Hurlocker

Dale L Krisher

Raymond E Tyrrell

William J Fox

William H Stephenson, Jr

Richard W Peters

Richard J Sanders, Jr

Stephen C Dunning

Gus C Sanders, Jr

Sahabettin C Demiray

Francis G Noser

Hal A Thorne

Jak Yaemsiri

Jeffrey P Jones

Keith L Bernhardt

O Lamar Bishop

M Rodney Briscoe

Kenneth J Stoia

V Paul Runyon

Heinrich T Sonnenberg

Patrick M Farrell

Victor W Wilkerson

Mohammad S Arani

Dana Merrill

Wenkwei Rou

Camille A Abu-Saba

Michael Sutton

A receive SONET line interface includes an elastic store which receives and stores incoming signals from a pointer tracking circuit and retrieves stored signals for providing to a pointer generating circuit wherein, for both the pointer tracking and pointer generating circuits, separate state memories are provided for keeping track of the state of previous state pointer tracking and generating signals in time slots of repetitive frames of an incoming SONET signal.

Time division multiplexed synchronous state machine having state memory

A SONET network element receives incoming SONET signals with a receive line interface (2) which stores the incoming data in an elastic store at the recovered line rate while a local interface reads the stored data at the local network element rate, which may vary slightly from the recovered line rate, and which adjusts the received pointers according to the difference between the line and local rates or phase, allowing the payload data to 'float' with respect to the boundaries of frames containing both payload data and overhead with pointers; an elastic store monitor performs the comparison between the receive payload rate and the local clock by comparing write addresses at the recovered line rate and read addresses at the local network element rate by a subtraction process which causes pointer adjustments to be made in response to the subtracted difference exceeding selected memory limits. A process for carrying out VT/TU and/or STS/STM pointer interpretation and generation is shown.

Sonet payload pointer processing and architecture

Read and write addresses on the local and line sides of a SONET elastic store are compared at least twice in order to determine any ambiguity in the comparison and, if so determined, foregoing any pointer adjustments that would otherwise have been made.

Sonet tributary ambiguity resolution for elastic store control

In a SONET-access product, channel-associated signaling is rearranged into SONET-formatted signaling, with the signaling for added channels being multiplexed with the signaling for through channels, in accordance with a control signal received from a channel map RAM, which stores one bit of data for each channel to indicated whether it is a through channel or an add channel. The RAM is provisioned by a network control processor.

Sonet transmit signaling translator

A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Synchronous optical transmission system

The four signaling bits contained in the eight-bit SONET signaling bytes are read from the SONET signaling row and are converted to four parallel signaling bits for storage in a RAM in quasi-SONET format, with sets of four A, four B, four C and four D bits for four consecutive channels being stored for an even and an odd tributary in one RAM memory row. Storing sets of four of the same bit for four consecutive channels simplifies the RAM write operation. A read-modify-write system is used for updating the RAM storage, wherein a row of RAM is read, modified by eight new signaling bits from two consecutive SONET signaling bytes, and is rewritten into the RAM. New signaling bits are stored to accumulate eight new signaling bits for two tributaries prior to updating the RAM with the new bits for both tributaries. The 32 signaling bits output during a RAM read operation are selectively multiplexed to output only four bits associated with a particular channel.

Sonet receive signaling translator

A system for aligning framing bits from independent digital transmission facilities with framing of a higher transmission rate facility includes a RAM memory. Received framing bits from the independent digital transmission facilities are stored at RAM locations in accordance with multiframe addresses of the framing bits relative to the multiframe format of the independent facility. Multiframe indicator bytes indicative of the framing of the higher transmission rate facility are used as addresses to read framing bits from RAM. The multiframe address of the independent digital transmission facilities is established by a counter for each independent facility, said counter being synchronized to the framing of the independent facility and incremented to provide addresses identical to the multiframe indicator bytes of the higher transmission rate facility.

System for aligning transmission facility framing bits to the sonet H4

A filtering algorithm for the SONET H4 byte is implemented with circuitry including an internal H4 counter which is incremented each frame and is locked to a received H4 byte once every 24 frames if a proper bit sequence is detected in a designated frame. If the designated bit sequence is not detected, the counter is not reset and continues to be incremented. If parity errors are detected, the counter is not reset and is allowed to free run to simulate the appropriate H4 byte input.

SONET 4h byte receiver and filter

An H4 byte generating algorithm is implemented by circuitry which includes counters for generating the H4 byte. The circuit is provisioned to indicate whether it is operating in a terminal multiplexer mode or an add-drop multiplexer mode. In the terminal multiplexer mode the counters are allowed to free run and continually produce successive H4 byte outputs. In the add-drop multiplexer mode selected counter outputs are compared with the received H4 byte and the number of mismatches is accumulated by a mismatch counter. When the mismatch counter reaches a predetermined number the value of the received H4 byte is loaded into the H4 byte counters and the mismatch counter is reset. Each time a proper match between H4 counter outputs and the received H4 byte is sensed, the mismatch counter is reset to 0. The presence of a red alarm will also result in the resetting of the mismatch counter and free running of the H4 byte counters.

Sonet H4 byte generator

Growing community of inventors

Raleigh, NC, United States of America

Ertugrul Baydar