Agate Logic, Inc.

Synopsys, Inc.

Ernst W Mayer

Steven Winegarden

Ronald H Nicholson, Jr

Greg Woolhiser

Haichun Chun

Kuldeep Karlcut

Wern-Jieh Sun

Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.

Tiered schematic-driven layout synchronization in electronic design automation

Methods for interconnecting base, switching and interconnect resources for configurable integrated circuits are provided, where these methods include the following steps: interconnecting base and switching resources with interconnect resources to form a hierarchical interconnect structure; physically placing the hierarchical interconnect structure in a two dimensional format; and directly interconnecting selected neighboring base and switching resources. The integrated circuits generated include base resources, interconnect resources; and switching resources that are interconnected to form a hierarchical interconnect structure, and, additional interconnect resources that directly interconnect neighboring switching or base resources.

Integrated circuits with hybrid planer hierarchical architecture and methods for interconnecting their resources

The present invention relates to methods for the global and detail routing of integrated circuits with hierarchical interconnect routing architecture. The methods includes the steps of: mapping routing resources of said integrated circuit to the nodes and edges of a graph theoretic tree, mapping each target to a target node; mapping each driver to a driver node; and routing each driver and its targets as a function of the minimum spanning tree spanning each driver node and its target nodes by traversing from the target nodes of a driver backwards toward its driver node in said tree. The methods of this invention are straightforward to implement, of polynomial time complexity, and can optimize routing resource usage.

Reverse routing methods for integrated circuits having a hierarchical interconnect architecture

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Cupertino, CA, United States of America

Ernst W Mayer