Siemens Aktiengesellschaft

Siemens Aktiengesellschaft & Semikron Gmbh

Ernst Hebenstreit

Roland Schreiber

Hermann Betzl

Leo Lorenz

Heinz Amann

Winfried Schierz

A discretely constructed MOSFET is switched by a voltage applied between gate terminal and source terminal. The source terminal has a self-inductance in which a fast change of the load current induces a considerable voltage which opposes the applied gate-source bias. This opposing voltage is reduced since the source contact is connected to an auxiliary terminal which is largely magnetically decoupled from the source terminal. A control voltage is applied between gate terminal and auxiliary terminal. When a plurality of MOSFETs are connected in parallel, oscillations in the control circuit can thus be effectively suppressed.

Semiconductor component having at least one power MOSFET

In power switches, conductive coupling of the control signal inputs to the power switching stage, and to the load to be switched, can result in impairment of control function. Moveover these power switches known in the art, have the disadvantage that the drive circuit and power switching stage must lie at the same potential. An improved self protecting power switch includes a first drive unit and a second drive circuit that are connected together via a pulse transformer. The first drive unit generates successive pulse trains in response to a control signal. A second drive unit regenerates square wave signals for the control of the power switching stage.

Circuit arrangement of a self protecting power switch

Power MOSFETs for switching high voltages have a relatively high on-state DC resistance. The invention provides for the connection in series of a low voltage MOSFET with a higher voltage bipolar transistor. This series circuit is connected in parallel with a series circuit consisting of another MOSFET and a threshold switch. The threshold switch is placed between the base terminal and the free terminal of the low voltage MOSFET. The MOSFETs receive a joint control signal (u.sub.1) which is routed to the low voltage MOSFET. In the case of an inductive load with recovery operation, the signal is routed through a delay element that becomes active when the circuit is turned on.

Combined bipolar and MOSFET switch

Circuit for controlling at least one power-FET, including a transformer having a primary and a secondary winding, a control input connected to the primary winding, a first terminal of the secondary winding connected to the gate electrode of the FET, at least one diode connected between the first terminal of the secondary winding and the gate electrode of the FET, a second terminal of the secondary winding connected to the source of the FET, a differential member connected between the control input and the primary winding, and a switch connected between the secondary winding and the gate electrode of the FET, the switch connecting the gate electrode of the FET to the first terminal of the secondary winding in the case of a given secondary signal of a first polarity, and the switch connecting the gate electrode of the FET to the source electrode of the FET in the case of a given secondary signal of a second polarity.

Circuit for controlling at least one power-FET

A switch includes an MIS-FET having a source and a control electrode defining a gate-source capacitance and being operated as a source follower for switching a given voltage, a first capacitor, a first auxiliary transistor and a second auxiliary transistor cutting off the first transistor when switched into a conducting state. The transistors each have a base, a collector and an emitter electrode defining a switching path. The collectors of each of the transistors are connected to the control electrode of the FET. A control input terminal is provided as well as second and third capacitors each being connected between the control input terminal and the base of a respective one of the transistors. The emitter electrode of the second transistor is connected to the source electrode of the FET. The first capacitor has one lead connected to the emitter electrode of the second transistor and to the source electrode of the FET for charging the gate-source capacitance of the FET through the switching path of the first transistor, and another lead connected to the emitter electrode of the first transistor and to a terminal of a voltage source having a lower voltage than the given voltage to be switched by the FET for charging the first capacitor when the first transistor is cut off.

Switch with an MIS-FET operated as a source follower

A linear output stage for charge-coupled circuits is disclosed. Charge-coupled circuits (CCDs) are of significance in the processing of analogue signals as they can be used as analogue shift registers. Conventional output circuits of CCDs are constructed with source followers. The non-linear characteristic of an MOS source follower which is provided with an external load resistor is substantially linearized by means of a highly ohmic source resistor. A fundamental disadvantage of these output circuits is that the evaluation of the signal is mainly carried out by means of a space charge capacitance which is voltage-dependent since it is dependent upon space charge depth. In the output stage disclosed, the signal charge is mainly absorbed by means of a constant oxide capacitance of the evaluator electrode. The electrode receives the charge not in floating fashion but rather at a fixed potential.

Linear output stage for charge-coupled circuits

A filter circuit utilizing charge transfer delay lines having individual CTD elements utilizing four-terminal resonators each of which is designated as a self-contained closed looped circuit and which determine the frequency dependent transmission characteristics of the filter circuit and wherein successive four-terminal resonators are interconnected by way of a coupling circuit. The invention utilizes the coupling circuit mounted between adjacent four-terminal resonators which are constructed simply as possible and utilizing integrated circuit techniques. Amplifiers are connected in parallel with the input and/or the output of the individual four-terminal resonators and the signal flow direction of the amplifiers corresponds to that of parallel connected CTD lines and the series lines of the coupling circuit and the amplifiers have unidirectional transmission characteristics and an inverting amplifier is contained in at least one of the series lines.

Electrical filter circuit utilizing charge transfer delay lines

An electrical filter circuit comprising charge transfer devices formed as lines consisting of individual CTD elements formed as four-terminal resonators formed as closed looped circuits and which determine the frequency-dependent transmission behavior of the filter circuit and wherein the four-terminal resonators are interconnected by way of a coupling circuit. In the invention, the filter circuit functions as a separating and shunt circuit and can be formed as an integrated circuit with two end resonators designed as self-contained closed looped circuits.

Electrical filter circuit utilizing charge transfer devices formed as

A resonator circuit formed in MOS technology for scanned analog signals, wherein such circuits are constructed for use with accumulators and information processing is accomplished by means of switched capacitors which are charged or respectively connected to each other by way of clock pulse transistors. In the present invention, the realization of general ladder networks or branching circuits for builders in single layer MOS techniques is accomplished by utilizing a second continuous branch which is switched to a first accumulator stage by clock pulse switches and is connected with a reference potential through a capacitor as well as to a further accumulator input through a series switch. The signal series arms are connected with the outputs of the total accumulator arrangement by way of time delay transit elements. The total accumulator arrangement is expanded to a resonator of the type of a four pole network having two inputs to which one respective transmission and one respective reflection output is assigned by utilizing difference elements and transfer elements. The arrangement of the invention is suitable for use as general branching filter circuits, and an increase of the dynamic range by better suppression of the clock pulse pickup and the harmonic distortion of the second order occurs by utilizing push-pull arrangements.

Resonator formed in integrated MOS technology utilizing switched

A read-out circuit for digital storage elements wherein a bit line can be connected to a storage capacitor which is connected to the input of a first inverting amplifier stage and the output of the amplifying stage is connected to the input of a second inverting amplifier stage and wherein the first amplifier stage can be bridged by way of a first switch and the output of the second amplifier stage can be connected to the input of the first amplifier by way of a second switch and wherein the input of the first amplifier stage and the output of the second amplifier stage are connected together by way of a capacitor.

Read-out circuit for digital storage elements

An integrated, programmable logic arrangement includes an AND matrix and an OR matrix which have individual gates. In the AND matrix each input is connected to a control line and via an inverter to another control line for production of a complementary input signal. A selector line and a base line are provided for each gate both in the AND matrix and in the OR matrix and the selector line is connectible to the supply potential. In the AND matrix, in programmed fashion, a switching transistor is provided at the intersection points between a control line and a selector line, or is not so provided, and a switching transistor so arranged at an intersection is connected by its gate terminal to an associated control line, Also, the switching transistor is connected, on the one hand, to an associated selector line of a gate and, on the other hand, to a base line which is connectible to another potential. The difference between the supply potential and the other potential corresponds to the supply voltage. In the OR matrix, in a correspondingly programmed fashion, a switching transistor is provided at an intersection point of a control line and a selector line or is not so provided. A switching transistor so provided is connected by its gate terminal to the associated control line and is connectible, on the one hand, to the selector line of a gate which may be connected to the supply potential and, on the other hand, to a base line which is connectible to ground. In the AND matrix a selector line of a gate is, in each case, connected by way of a pulsed load transistor to the supply potential and the base line of the gate is connectible by way of a pulsed cut-off transistor to the further potential. In the OR matrix, in corresponding fashion, a selector line of a gate is, in each case, connectible via a pulsed load transistor to the supply potential and the base line of the gate is connectible via a pulse cut-off transistor to the further potential. A pulsed flip-flop is arranged, in each case, between an output of the AND matrix and an input of the OR matrix and a pulsed flip-flop is provided, in each case, at an output of an OR matrix.

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Munich, Germany

Ernst Hebenstreit