Infineon Technologies Ag

International Business Machines Corporation

United Microelectronics Corp.

Infineon Technologies North America Corp.

United Microelectronics Co.

United Mircroelectronics Co.

Ernst H Demm

Robert C Wong

Pak Leung

Alexander M Hirsch

Sun-Oo Kim

Thomas W Dyer

Rajendran Krishnasamy

Jin-Ping Han

A semiconductor interconnect architecture provides a reduction in the intersection of vias on the last layer ('VL') and holes in the last thin metal layer ('MLHOLE') without degradation of the product yield or robustness, or increases copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Generation of metal holes by via mutation

A reduction in the intersection of vias on the last layer ('VL') and holes in the last thin metal layer ('MLHOLE') can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.

Method of producing a semiconductor interconnect architecture including generation of metal holes by via mutation

There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.

Channel strain engineering in field-effect-transistor

A method of forming a metal-insulator-metal (MIM) capacitor wherein a plate of a MIM capacitor is formed in the entire thickness of a metallization layer of a semiconductor device. At least one thin conductive material layer is disposed within the material of the metallization layer to reduce the surface roughness of the metallization layer, thus improving the reliability of the MIM capacitor. The thin conductive material layer may comprise TiN, TaN, or WN and may alternatively comprise a barrier layer disposed over or under the TiN, TaN, or WN. One plate of the MIM capacitor is patterned using the same mask that is used to pattern conductive lines in a metallization layer, thus reducing the number of masks that are required to manufacture the MIM capacitor.

MIM capacitor structure and method of fabrication

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Putnam Valley, NY, United States of America

Ernst H Demm