International Business Machines Corporation

Globalfoundries Inc.

Ernest Y Wu

Baozhen Li

Andrew Tae Kim

Chih-Chao Yang

Nazmul Habib

Emmanuel Yashchin

Pascal A Nsame

Carole D Graas

John Greg Massey

Deborah M Massey

Barry P Linder

James H Stathis

Alvin Wayne Strong

Edward J Nowak

Kerry Bernstein

Ronald Jay Bolam

Jody John Van Horn

Takashi Ando

Junli Wang

Dechao Guo

Ruqiang Bao

Heng Wu

Griselda Bonilla

Peilin Song

Franco Stellari

William A Klaasen

Kai Zhao

Jim Shih-Chun Liang

Steven W Mittl

Roger Aime Dufresne

David G Brochu, Jr

System and method to localize a position of an RRAM filament of resistive memory device at very low bias voltages using a scanning laser beam. The approach is non-invasive and allows measurement of a large number of devices for creating statistics relating to the filament formation. A laser microscope system is configured to perform a biasing the RRAM cell with voltage (or current). Concurrent to the applied bias, a laser beam is generated and aimed at different positions of the RRAM cell (e.g., by a raster scanning). Changes in the current (or voltage) flowing through the cell are measured. The method creates a map of the current (or voltage) changes at the different laser positions and detects a spot in the map corresponding to higher (or lower) current (or voltage). The method determines the (x,y) position of the spot compared to the edge/center of the RRAM cell.

RRAM filament spatial localization using a laser stimulation

A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.

Reliable resistive random access memory

Metal e-fuse structure formed during back-end-of-line during processing and integral with on-chip metal-insulator-metal (MIM) capacitor (MIMcap). The metal e-fuse structures are extensions of MIMcap electrodes and are structured to isolate BEOL MIM capacitors for trimming and/or to isolate shorted or rendered highly leaky due to in process, or service induced defects. In one embodiment, the method incorporates the integral, co-processed metal e-fuse in series between the MIM capacitor and an active circuit. When a high current passes through the e-fuse element, the e-fuse element is rendered highly resistive or electrically open thereby disconnecting the MIM capacitor or electrode plate from the active circuitry. The e-fuse structure may comprise a thin neck portion(s) or zig-zag neck portion that extend from an MIMcap electrode away from the MIMcap between two inter-level interconnect via structures.

E-fuse co-processed with MIM capacitor

An e-Fuse device including a first electronic feature and a second electronic feature comprised of a conductive material, each of the first electronic feature and the second electronic feature having a width at least as great as a ground rule of a patterning process; and a fuse element comprised of the conductive material having a width less than the ground rule of the patterning process, the fuse element connecting a bottom portion of the first electronic feature and a bottom portion of the second electronic feature. Also disclosed is a method of making the e-Fuse device.

Sub-ground rule e-Fuse structure

A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Optimization of integrated circuit reliability

A mandrel structure includes a first mandrel, a second mandrel and a third mandrel in a parallel arrangement. The second mandrel is located between the first and third mandrels and has a cut larger than a minimum ground rule feature. A sidewall layer is formed over the mandrel structure. The sidewall layer has two long parallel gaps for two contact lines and a third gap for a fuse element. The third gap is orthogonal to and connects the two long parallel gaps. The sidewall pattern is used to form a trench structure comprising two parallel contact line trenches having a width at least as great as a ground rule of the patterning process for the contact lines and an orthogonal fuse element trench having a width less than the ground rule for the fuse element. A conductive material forms the contact lines and a fuse element.

Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.

Semiconductor device having two-part spacer

Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.

BEOL thin film resistor

A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.

Graded interconnect cap

A three plate MIM capacitor structure includes a three plate MIM capacitor, a first wire in a metal layer above/below the three plate MIM, a second wire below/above the three plate MIM, a third wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first wire and the second and third wires or detecting leakage current across the second wire and the third wire.

Three plate MIM capacitor via integrity verification

A three plate MIM capacitor test structure includes a three plate MIM capacitor, a first test wire in a metal layer above/below the three plate MIM, a second test wire below/above the three plate MIM, a third test wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first test wire and the second and third test wires or detecting leakage current across the second test wire and the third test wire.

Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.

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Essex Junction, VT, United States of America

Ernest Y Wu