Analog Devices,inc.

Other

Ernest T Stroud

Rodney Dean Miller

Tyre Paul Lanier

Ted Hecht, Jr

Jinhjiang Yin

David C Reynolds

David H Robertson

Douglas A Mercer

David T Crook

George F Diniz

A digital video interface receiver adjusts a transfer function of a phase-locked loop circuit having a programmable charge pump, a programmable phase-locked loop filter, or a programmable gain voltage controlled oscillator. The digital video interface receiver monitors and detects errors in a data stream associated with the phase-locked loop circuit. Moreover, the digital video interface receiver changes the transfer function of the phase-locked loop circuit, in response to the detected errors, by changing parameters associated with the programmable charge pump, the programmable phase-locked loop filter, or the programmable gain voltage controlled oscillator of the phase-locked loop circuit so as to change the transfer function of the phase-locked loop circuit.

Adaptable phase lock loop transfer function for digital video interface

Phase-locked loop structures are provided that facilitate enhanced stability of loop-generated signals. They include an oscillator network, a feedback loop and a controller. The oscillator network generates a loop output signal with a frequency that varies in response to a control voltage and to a frequency-determining parameter, the feedback loop generates the control voltage in response to the loop output signal and a reference signal and the controller increments the frequency-determining parameter to maintain the control voltage within a predetermined control-voltage range. These structures enhance signal stability by facilitating the use of low-gain oscillator structures and they simplify and shorten loop operations because the structures operate in a closed-loop condition at all times.

Phase-locked loop structures with enhanced signal stability

A &pgr;/4 DQPSK modulator includes a rotated and offset &pgr;/4 encoder that provides encoded I, Q constellation indices values using positive integers. The positive integer I and Q values are input to a digital filter that provides filtered I, Q constellation indices values. These filtered values are then rotated and offset back to conventional &pgr;/4 DQPSK constellation values, modulated and transmitted. Since the rotated and offset &pgr;/4 encoder provides I, Q constellation indices as positive integers, the filters are implemented as multiplierless digital filters which significantly reduces the complexity of the filters. Specifically, the multiplierless digital filters can be implemented using shift registers and summers. In a preferred embodiment the filters are programmable. In addition, using positive integers to represent the rotated and offset &pgr;/4 signalling constellation indices allows the indices to be represented as a binary value with less bits in contrast to prior art systems. Significantly, representing the indices with less bits further reduces the complexity of the digital filters.

&pgr;/4 DQPSK encoder and modulator

A drive circuit and method for shaping the pair of complementary digital signals that drive a conventional CMOS switch are presented. The method adjusts the digital signals' duty cycles to set their cross point voltage levels so that at the cross points the voltage level at the CMOS switch's reference node is undisturbed with respect to its fully switched level. The drive circuit includes two pair of diode connected PMOS load transistors and NMOS load transistors that are connected at a pair of output terminals and a pair of switches. In one state, the NMOS load transistor is turned on while the switch cuts off its signal current so that the shaped digital signal's voltage at the output terminal is reduced to a precision limited low voltage. In the other state, the NMOS load transistor is turned off while the switch directs the signal current through the PMOS load transistor so that the shaped digital signal's voltage at the output terminal is increased to the PMOS load transistor's gate-to-source voltage. The CMOS transistors' channel geometries and the amount of signal current are selected to set the duty cycle of the shaped digital signals and thereby set the optimum cross point voltage levels.

Drive circuit and method for controlling the cross point levels of a

A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.

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Greensboro, NC, United States of America

Ernest T Stroud