International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Ernest Nelson Mandese

Richard N Mendelson

Francis M Bonevento

Howard J Locker

Daryl Carvis Cromer

James Peter Ward

Sameh W Asaad

Bengt-Olaf Schneider

Kevin Wilson Warren

Andrew B McNeill

Jan Michael Janick

Nicholas R Dono

Dhruvkumar M Desai

Sammy D Dodds

Rod D Waltermann

David Carroll Challener

Chester A Heath

Richard Wayne Cheston

Joseph Michael Pennisi

Dhruv Manmohandas Desai

John K Langgood

Douglas R Chisholm

Joaquin F Pacheco

Hernando Ovies

Timothy J Louie

Joseph P McGovern

Michael Douglas Anderson

Kerry Graham Sanders

Douglas R Chrisholm

Arthur J Heimsoth

When a media error occurs on a storage device of a number of storage devices of a redundant array, the logical stripe of data affected by the media error is determined. A portion of non-volatile memory is reserved and the logical stripe is backed up to this portion of non-volatile memory. A read request is subsequently serviced from the non-volatile memory and not from the storage devices. When a write request is received, it is first serviced to the storage devices. If successful, then the previously reserved portion of non-volatile memory is freed up, and subsequent requests are serviced using the storage devices. If unsuccessful, then the write request is serviced using the non-volatile memory.

Raid logical stripe backup to non-volatile memory in response to raid storage device media errors

Initially, a hardware inventory device is provided within the data processing system. UIC that uniquely identifies the data processing system is stored in a non-erasable memory of the hardware inventory device. An encrypted hash generated by combining the UIC and a BIOS hash is stored in the non-erasable memory of the hardware inventory device. In response to a loading of a software program previously installed within a direct access storage device of the data processing system, the following steps are performed: i. the encrypted hash is obtained from the non-erasable memory of the hardware inventory device; ii. the encrypted hash is decrypted; iii. a new hash is generated by using the UIC and a BIOS from the data processing system, and the decrypted hash is compared with the new hash; and iv. the software program loading is allowed to continue when the decrypted hash matches the new hash.

System and method for data processing system planar authentication

Access to secure data through a portable computing system is provided only when a timer within the system is running. The timer is reset with the portable system connected to a base system, either directly, as by a cable, or indirectly, as through a telephone network. In an initialization process, the portable and base systems exchange data, such as public cryptographic keys, which are later used to confirm that the portable system is connected to the same base system. In one embodiment, the initialization process also includes storing a password transmitted from the portable system within the base system, with this password later being required within the reset process.

System and apparatus for limiting access to secure data through a portable computer to a time set with the portable computer connected to a base computer

A computer system, includes a mobile computer, a docking station for receiving the mobile computer, a bridge having a first side coupled to the mobile computer and a second side coupled to the docking station, and a flat panel display formed with the docking station for being coupled to the mobile computer via the docking station. The docking station includes a dock housing coupled to a desktop display and including a first bus, and a bridge coupled between the first bus and a second bus, the first bus residing in the dock housing and the second bus for being coupled to the mobile computer.

All-in-one mobile docking station and system used therewith

A computer network system includes a plurality of computers each including a central processing unit (CPU), a memory and at least one peripheral device, a connection fabric having selectable first and second sides, the first side being coupled to a first computer of the plurality of computers and the second side being coupled to at least a second computer of the plurality of computers. Each of the first and second computers performs a negotiation to determine which one of the first and second computers controls resources of the other of the first and second computers.

System and intelligent dock using a symmetric extended bus bridge and method therefor

A method and system for eliminating peripheral device conflicts in a multibus data-processing system which includes a Peripheral Component Interconnect (PCI) plus having multiple slots for interconnecting peripheral devices in an automatically derived configuration and an Industry Standard Architecture (ISA) bus having multiple slots for interconnecting peripheral devices in a user-selected configuration. Each slot included within the ISA bus includes a reset line for temporarily disabling an associated slot in response to an application of electrical power to the data-processing system in order to prevent power transition problems. In response to an existing or potential device conflict brought about by a user-selected configuration, a control signal is selectively applied to the reset line for one or more slots included within the ISA bus, temporarily disabling those slots during normal operation of the data-processing system.

Method and system for selective disablement of expansion bus slots in a multibus data processing system

Multiple PCI adapter cards are supported by a single PCI slot through the aspects of the present invention. A computer system aspect includes an &mgr;ATX planar including at least one PCI slot, and a riser card mounted in the at least one PCI slot, the riser card supporting multiple PCI adapter cards and providing signal generation to allow the multiple PCI adapter cards to utilize the at least one PCI slot. The riser card aspect includes a PCI connector for coupling to a PCI slot on the &mgr;ATX planar, a plurality of PCI slots for attaching a plurality of PCI adapter cards, and a logic device for providing separate bus signal pairs to each of the plurality of PCI adapter cards from a single signal pair of the PCI slot on the &mgr;ATX planar.

Multiple PCI adapters within single PCI slot on an matax planar

Described is a computer system which is coupled to a remote computer via a network cable. The computer system has a normally closed enclosure and is capable of securing data retained within the system against unauthorized access. The computer system includes an erasable memory element mounted within the enclosure for selective activation to active and inactive states and for receiving and storing a security password when in the active state. A manually operable option switch is mounted within the enclosure. The option switch is operatively connected with the erasable memory element and manually settable by a user of the computer system for setting the erasable memory element to the active and inactive states. A cable removal detector is coupled to the enclosure and is operatively connected with the erasable memory element for detecting a disconnection of the cable and for clearing any stored security password from the erasable memory element in response to any switching of the cable removal detector between a first state and a second state.

Computer system and method to disable same when network cable is removed

A coded logical interrupt signal is sent between system or subsystem units in a data processing system. The logical interrupt is sent by a sending unit, that requests the interrupt, and is sent to a receiving unit that the sending unit wishes to interrupt. These coded logical interrupts are accumulated in the receiving unit. When the receiving unit is actually physically interrupted by control of the processor in the unit, all logical interrupts that have been accumulated are processed. The logical interrupt may be coded to indicate sending unit, that is the source of the interrupt, and the action being requested by the sending unit. If the interrupt includes only source information, the action information is sent separately by the sending unit to memory in the receiving unit. If the interrupt includes both source identification and action information, the receiving unit can interpret source and action directly from the interrupt.

Peer to peer computer-interrupt handling

This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus. An interrupt controller is coupled to the microprocessor and bus for recognizing delivery of an interrupt signal and for periodically generating an interrupt reset signal and delivering reset signals to all of the input/output devices simultaneously for setting all of the devices to a condition indicative of no request for access to said microprocessor.

Personal computer system with interrupt controller

A computing system including a host processor and at least one intelligent subsystem having attached devices, has two interrupt ports. The one intelligent subsystem and the attached devices are each viewed as a logical device by the host processor, and each is assigned a device identification number. The host processor provides direct and indirect commands to the logical devices. For direct commands, first physical interrupts are provided to the host processor serially from the logical devices through an Interrupt Status Port. For indirect commands, logical interrupts are stored in predetermined bit positions in a Device Interrupt Indentifier Port (DIIP) in accordance with the device identification numbers. A second single physical interrupt is provided to the host processor as long as there is at least one logical interrupt pending from at least one logical device as the result of an indirect command. The host processor reads the DIIP to determine which logical devices have at least one logical interrupt pending for an indirect command. A plurality of logical interrupts for a single logical device may be cleared with a single reset interrupt command from the host processor.

Interrupt handling for a computing system with logical devices and

A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Command delivery for a computing system for transferring data between a

A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Growing community of inventors

Durham, NC, United States of America

Ernest Nelson Mandese