International Business Machines Corporation

Siemens Aktiengesellschaft

Kabushiki Kaisha Toshiba

Siemens Components, Inc.

Ernest N Levine

Nancy Anne Greco

James Gardner Ryan

Michael F Lofaro

Jeffrey P Gambino

Stephen Edward Greco

Robert F Cook

Thomas H Ivers

Eduardo Garcia

Anthony K Stamper

Daniel C Edelstein

John Anthony Fitzsimmons

Thomas M Shaw

Xiao Hu Liu

Conal Eugene Murray

Hyun K Lee

Vincent James McGahay

Paul Charles Jamison

Christopher P Ausschnitt

Hormazdyar M Dalal

Michael Wayne Lane

Darryl D Restaino

Hazara Singh Rathore

Klaus Hummler

Mark A Jaso

Munir D Naeem

Du Binh Nguyen

Birendra N Agarwala

Masaki Narita

Donna Rizzone Cote

Peter D Hoh

Jawahar P Nayak

Norbert Arnold

Glenn A Biery

Virinder Grewal

Stuart M Burns

Horatio Quinones

Bruno Spuler

Lewis D Lipschutz

Ann H McDonald

Edward Paul Barth

Pei-Ing Paul Lee

Conrad A Barile

Brett H Engle

John F McGrath

Parth P Dave

Steve Greco

Bettina A Dinkel

Rainer Weiland

A metallization insulating structure, having

Dual damascene interconnect structure using low stress fluorosilicate insulator with copper conductors

A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

Stacked via-stud with improved reliability in copper metallurgy

A lithographic process for creation and replication of well-controlled surfaces of arbitrary profiles on a sub-micron scale. The surfaces are defined by a mathematical function using a binary mask, consisting partly or wholly of subresolution features, and a photoresist film of pre-specified absorption and thickness. The process comprises the steps of (a) creating a mask, (b) imaging the mask pattern on an absorbing photoresist film to a predetermined thickness, and (c) transferring the three dimensional surface to a substrate.

Micro-surface fabrication process

The adhesion of a silicon carbide containing film to a surface is enhanced by employing a transition film of silicon nitride, silicon dioxide and/or silicon oxynitride.

Adhesion of silicon carbide films

A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes. Via holes may be etched to contact a micro pipe, or to inter connect micro pipes buried at different levels Thus, instead of eliminating defective voids in trenches, the voids are controlled to form the micro pipes, which may be used to circulate a cooling fluid, or lined with a conductive material to form a micro light pipe channel, or buried conductive pipes.

Manufacturing methods and uses for micro pipe systems

An aid to the manipulation of microfabricated micro tools in manufacturing and assembly is disclosed. A sequence of micro tools and a manipulator are connected to one another via attachment links as a combination. The attachment links are optimized to readily allow severing of individual micro tools from the combination as needed. The manipulator provides an aid for handling the combination via probe, pliers, clasping, mating or other device. This facilitates human or machine interaction with the combination of micro tools, either for subsequent processing, or for the assembly of the micro tools into a completed product.

Manipulation of micromechanical objects

A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Low temperature via fill using liquid phase transport

The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.

Method for producing a crack stop for interlevel dielectric layers

A seamless micromechanical object is cast by forming a multilevel mold, filling the mold, and selectively removing the mold with respect to the micromechanical object. The mold can have a first level having a first opening therein, and a second level on the first level, the second level having a second opening therein, the second opening smaller than the first opening. The object may contain a controlled void, for example a micromechanical auger with a void formed therethrough to be used as a capillary to drain off fluids when the auger is in use.

Casting of complex micromechanical objects

Integrated circuit having crack stop for interlevel dielectric layers

A metal layer is formed at high deposition rate over severe topography by a two step process including formation of a seed layer by cold deposition followed by a second portion of the metal layer deposited at a temperature approximating but below a temperature at which metal from a lower metal layer can extrude through vias reaching thereto. The seed layer is preferably limited to a thickness at which the conformality of the cold-deposited metal will not significantly increase severity of surface topography, generally about one-fourth the thickness of the hot-deposited layer. Via connections are formed without voids and a more planar metal layer surface is formed which allows formation of a protective/anti-reflective layer with good integrity while enhancing subsequent lithographic patterning, thereby eliminating alteration of metal surface chemistry by resist developers and resultant residual metal included within the severe topography.

Metal deposition process for metal lines over topography

A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes. Via holes may be etched to contact a micro pipe, or to inter connect micro pipes buried at different levels. Thus, instead of eliminating defective voids in trenches, the voids are controlled to form the micro pipes, which may be used to circulate a cooling fluid, or lined with a conductive material to form a micro light pipe channel, or buried conductive pipes.

Semiconductor structures containing a micro pipe system therein

A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.

Methods for metal etching with reduced sidewall build up during

An energy relieving, redundant crack stop and the method of producing the same is disclosed. The redundant pattern allows the crack propagating energy that is not absorbed by the first ring of metallization to be absorbed by a second area of metallization and also provides a greater surface area over which the crack producing energy may be spread. The redundant crack stop is produced during the metallization process along with the rest of the wiring of the chip surface and, therefore, no additional production steps are necessary to form the structure.

Energy relieving crack stop

A method is disclosed for locating a particular small objects (down to submicron) within an array of periodically arranged like objects utilizing a scanning tool. The method includes scanning the array for generating a plurality of pulses, which correspond to these objects contained within the array. Counting the plurality of pulses in order to locate the particular object within the array.

Automated non-visual method of locating periodically arranged sub-micron

Growing community of inventors

Poughkeepsie, NY, United States of America

Ernest N Levine