Mips Technologies, Inc.

Ernest Lewis Edgar

Radhika Thekkath

Franz Treue

Richard T Leatherman

Bruce J Ableidinger

Neal S Stollon

A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is completed. A trace record is formed during tracing. The trace record includes a processor mode indication, application space identity value and an instruction architecture set mode indication.

External trace synchronization via periodic sampling

An embedded system or system on chip (SoC) includes a secure JTAG system and method to provide secure on-chip control, capture, and export of on chip information in an embedded environment to a probe. In one embodiment, the system comprises encryption logic associated with a JTAG subsystem and decryption logic in the probe for encrypted JTAG read traffic. Inverted encryption/decryption logic provides bi-directional encryption and decryption of JTAG traffic. Encrypted information includes both authentication of valid probe/target interface and encryption of debug data.

System debug and trace system and method, and applications thereof

A method of tracing processor data includes receiving a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock. The first trace stream is routed to a first dual-port synchronous memory in accordance with the first clock and the second trace stream is routed to a second dual-port synchronous memory in accordance with the second clock. The first trace stream and the second trace stream are delivered to a memory in accordance with a third clock.

Apparatus and method for tracing processor state from multiple clock domains

A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node.

Hyperjtag system including debug probe, on-chip instrumentation, and protocol

HyperJTAG system including debug probe, on-chip instrumentation, and protocol

A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

A system and method for program counter and data tracing is disclosed. Generated trace messages are included within a trace word format and stored in trace memory, thereby enabling a reduction in the amount of trace storage required.

Growing community of inventors

Larkspur, CO, United States of America

Ernest Lewis Edgar