Sifive, Inc.

Ernest L Edgar

Wesley Waylon Terpstra

Henry Cook

Ryan Macdonald

Yann Loisel

Bruce Ableidinger

Systems and methods are disclosed for debug in a system on a chip with a securely partitioned memory space. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions, including a data store configured to store a first world identifier; an outer memory system configured to store instructions and data; a data store configured to store a debug world list that specifies which world identifiers supported by the integrated circuit are authorized for debugging; and a debug enable circuitry configured to generate a debug enable signal based on the first world identifier and the debug world list, wherein the processor core is configured to jump to debug handler instructions in response to a debug exception or ignore the debug exception depending on the debug enable signal.

Debug in system on a chip with securely partitioned memory space

A trace circuitry may be configured to receive a selection of one or more types of events possible in a processor core among multiple types of events. The trace circuitry may generate a message including trace information when an event corresponding to the selection occurs in the processor core. The trace information may include an address associated with the event and an indication of the type of event and/or cause for why the event occurred. In some implementations, the trace circuitry may use an event filter to pass events corresponding to the one or more types of events that are selected and block events corresponding to one or more types of events that are not selected. In some implementations, the trace circuitry may generate timestamps based on events to enable measurements between the events.

Trace encoder with event filter

Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

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Colorado Springs, CO, United States of America

Ernest L Edgar