Intel Corporation

Ibtel Corporation

Ernest Knoll

Eyal Fayneh

Tsvika Kurts

Efraim Rotem

David I Poisner

Krishnakanth Venkata Sistla

Alon Naveh

Alexander Gendler

Michael Mishaeli

Ofer Levy

Jorge Pedro Rodriguez

Daniel J Ragland

Ofer J Nathan

Ariel Szapiro

Roni Ashuri

Ariel Gur

Ariel Sabba

Yoav Ben-Raphael

Yossi Ben Simon

Shani Rehana

Ariel Elad Avital

Brad M Dendinger

Gustavo Maba

Arkady Vaisman

Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.

Device, system and method to detect clock skew

Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

Techniques in phase-lock loop configuration in a computing device

Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Changing the clock frequency of a computing device

Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.

Delay stage with controllably variable capacitive load

An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C) state, and the processor may quickly exit to a Cstate in response to a bus event such as a bus snoop.

Method and apparatus for controlling power management state transitions

An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Startup/yank circuit for self-biased phase-locked loops

A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than +/&#x2212;1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.

High-accuracy continuous duty-cycle correction circuit

Yank detection circuit for self-biased phase locked loops

A method for controlling a phase-locked loop includes receiving a frequency change signal and electrically isolating a VCO control node of the phase-locked loop from at least one charge pump of the loop. During this isolation period, the VCO control node voltage is held at a constant value equal to the voltage that existed before the frequency change signal was received. One or more parameters of the PLL are then altered in a manner that will ensure generation of a newly desired output frequency. These parameters include but are not limited to a feedback divider value and a reference frequency input into the PLL. The new output frequency may be above or below the pre-change signal frequency depending, for example, on a mode of operation of a host system. When the VCO control node is once again electrically connected to the charge pump, the PLL locks on to the desired output frequency. Through this method, frequency change is accomplished without performing a startup process and the time to perform a frequency acquisition process is significantly reduced.

Method for clock generator lock-time reduction during speedstep transition

A charge pump includes a charge circuit switch, a pump circuit switch, and a controller for generating a first control signal for switching the charge circuit switch and a second control signal for switching the pump circuit. In order to reduce the effects of self-jitter and improve signal quality, the controller generates the first and second control signals so that they have a same amplitude and slew rate. This results in improving steady-state phase error (DC skew). To further improve performance, current sources of the charge pump are controlled to operate continuously. This advantageously minimizes parastic switching currents. The charge pump may be incorporated within a phase-locked loop for purposes of generating frequency signals. The phase-locked loop may be self-biased. A processing system having, for example, a microprocessor-based computing architecture may advantageously include the phase-locked loop for performing any one of a variety of applications.

High-performance charge pump for self-biased phase-locked loop

An on-chip, e.g., on a microprocessor, super filter-regulator acts as a voltage regulator and a low-pass filter. The voltage regulator generates a constant DC output voltage and regulates the DC voltage against instantaneous load changes. The low-pass filter and actively filters AC interference out of the DC output voltage. The super filter-regulator provides the filtered and regulated DC voltage to a phase locked loop circuit.

On-chip filter-regulator, such as one for a microprocessor phase locked loop (PLL) supply

A loop filter in the phase-locked loop includes a capacitor having a specific capacitance value. The loop filter also includes an amplifier coupled to a node of the capacitor. The amplifier amplifies a signal at the node in a way that increases the equivalent capacitance value without physically changing the capacitor.

Adaptive integrated PLL loop filter

A frequency divider includes an output-and-control-signals generation circuit. The output-and-control-signals generation circuit outputs an output clock signal and a control signal responsive to an input clock signal and a state signal. A shift register, characterized by having a count-sequence length of 2 &minus;1, outputs the state signal responsive to the output clock signal. A feedback loop is associated with the shift register. An exclusive or (XOR) gate, a multiplexer, and a plurality of flip-flops are disposed within the feedback loop. The multiplexer has a first input and a second input. A parallel-to-serial-input generation circuit is coupled to the output- and control-signals generation circuit and to the shift register, and receives the control signal. The first input of the multiplexer is coupled to the shift register and the second input of the multiplexer is coupled to the parallel-to-serial-input generation circuit.

Frequency divider

A self-biased phase-locked loop circuit includes a phase detector, first and second charge pumps, first and second loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency in response to the control signal. The second loop filter capacitor considerably improves the output clock jitter.

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Haifa, Israel

Ernest Knoll