International Business Machines Corporation

Ernest H Millham

Ronald J Prilik

John James Shushereba

John J Moser, Jr

Ralph J Scaccia

Steven H Foreman

Gary P Visco

James E Ortloff

Francis J Villante

A timing generator for generating a plurality of pulse sequences within a test cycle. Each pulse sequence has a plurality of pulses having a position identified by the data contents of a multiplicity of random access memories. Like numbered lower order bits of each memory are decoded to provide a plurality of pulse sequences corresponding in number to the number of lower order bits. The memories are arranged in a hierarchy. The random access memories are each provided with a separate address counter. The highest order bit of each memory is used to reset the respective memory address counter as well as enable an adjacent higher order memory address counter, and are decoded to define the end of the test cycle.

Timing generator for generating a multiplicty of timing signals having

Apparatus for applying for a plurality of test cycles data specifying a plurality of test conditions to a multiple pin electronic circuit. A random access memory includes at a plurality of higher order addresses a complete data field for a plurality of test cycles. Some of said data fields include an operational code indicating that a minority of data bits in a field are to change in a consecutive number of following test cycles. A hold register is connected to receive each addressed row of test data from the memory. The higher order addresses of a memory addressed to produce complete data fields in the hold register. An operational code will be decoded to indicate a number of subsequent consecutive test cycles where a minority of data in the hold register are to be changed. The lower order addresses of the memory are subsequently addressed for a number of consecutive test cycles indicated by the operational code. The data contained in the lower order memory addresses is inserted in the hold register without changing the contents of a majority of hold register data bits.

Apparatus for reducing test data storage requirements for high speed

A hierarchical complex logic tester architecture is disclosed which minimizes the encoding of program information for testing. The architecture takes advantage of the fact that much of the information applied as test signals to pins of a device under test, changes little from test cycle to test cycle. In one aspect of the invention, run length encoding techniques are used for identifying the number of test cycles over which a given test pin is to be maintained in a particular signal state. In another aspect of the invention, use is made of a small memory associated with each signal pin of the device to be tested. There may be a small plurality of for example, 16 different kinds of signals which can be applied to or received from a given signal pin of a device under test. The dedicated small memory associated with each device pin to be tested, will have the ability to store from one to 16 states. The current states stored in a dedicated-per-pin memory will enable one of the 16 different types of test signals per test cycle to be applied to the particular device pin. Thus, the types of signal driving or sensing for each of the plurality of pins for a device under test, need only be indicated once to the per-pin-memory over a large plurality of test cycles. This enables consecutive test cycles to be applied to the device under test under the control of a relatively small number of tester program words.

Hierarchical test system architecture

A technique is disclosed for locating the exact machine cycle, in a cyclic operation for a data processor, where an error occurs. Each cycle of the data processor is identified and counted as a cycle where the machine stopped with an error indication that is recorded. The cycles are then all caused to reoccur up to the cycle just preceding that cycle recorded and the machine is caused to stop without allowing the recorded cycle to occur. At this point it is determined whether an error did in fact occur. If an error did in fact occur, then the procedure is repeated, each time allowing the system to process to one cycle less than the preceding last cycle, until the error is no longer present. At this point, the true cycle with which the error occurs is identified as the next cycle just following the last one at which the processor was stopped. The technique may be augmented by suppressing error detections for the cycle so identified, and advancing the processor to succeeding cycles to determine whether any succeeding cycle also generates errors.

Dynamic error location

Logic and analog functions in a complex semiconductor component are stuck fault and parametrically tested through an analog/digital measurement adapter coupled to logic and analog testers. Both logic and analog testers are under computer control whose purpose is to direct the testing sequence, log test results, perform algorithmic calculations on the data and diagnose failing devices in the component under test. The adapter provides the electrical environment to match a range of components under test to the logic and analog testers. The adapter is also under computer control to permit impedance matching of a multiplicity of digitally controlled stimulus/response units connected through a multiplexor to the range of components under test.

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Catlett, VA, United States of America

Ernest H Millham