International Business Machines Corporation

Ernest Bassous

Subramanian Srikanteswara Iyer

Jean-Marc Halbout

Lawrence Kuhn

Vijay P Kesan

Bernard S Meyerson

Arnold Reisman

Michael R Scheuermann

Kevin J Uram

Howard Hyman Taub

Carlton M Osburn

Rajiv V Joshi

Tak H Ning

Kevin K Chan

Frank Daniel Egitto

David Brian Stone

Natalie Barbara Feilchenfeld

Elizabeth F Foster

Stephen Joseph Fuerniss

James Steven Kamperman

Gobinda Das

Johannes M Stork

Gary L Patton

Cheng-Yih Liu

Joseph M Blum

Donald J Mikalsen

Istvan Lovas

Alan D Wilson

Marvin B Skolnik

Constantino Lapadula

Peter Pleshko

Carl Altman

Angela C Lamberti

Massimo A Ghioni

Disclosed is a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a novel fixture for holding the substrate and a novel mask for 1-step photolithographic exposure. The result of the invention is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.

Gray scale etching for thin flexible interposer

Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity. The interdigitated pattern is then etched through the oxide film by lithography to expose the Si surface and metallic electrode members are formed selectively in the exposed Si surface, using self-aligned metallization to produce thin interdigitated electrodes recessed below the silicon surface, which itself may be on a comparatively thin Si layer. The electrodes may be spaced to minimize the interdigital carrier transit time and maximize the sensitivity and the entire process and structure are compatible with conventional silicon integrated circuit (IC) technology. A further feature involves isolating the semiconductor surface layer from the substrate by a layer that may be either 1) transparent and insulating, 2) optically absorbing, or 3) optically reflecting, so that the photocarriers recombine before they can be collected by the field. In the latter case, the photodetector acts as a resonant cavity, resulting in an increase in the number of carriers that are generated, and hence a more sensitive device.

High speed silicon-based lateral junction photodetectors having recessed

A system for making porous silicon on blank and patterned Si substrates by 'immersion scanning', particularly suitable for fabricating light-emitting Si devices and utilizing an open electrolytic cell having a cathode and an opposing anode consisting of a Si substrate on which the porous silicon is to be formed, both disposed, with their opposing surfaces in parallel, in an aqueous HF solution electrolyte contained in the cell. The substrate anode is mounted to be movable relative to the electrolyte so as to be mechanically cycled or scanned in and out of the electrolyte at a programmable rate during anodization. The uniformity, thickness and porosity of the resulting anodized layer on the substrate are determined by the scanning speed, number of cycles, current density, and HF-based electrolyte parameters of the system, and the Si substrate resistivity, conductivity type, and crystal orientation. The light-emitting silicon devices produced incorporate porous silicon layers and are operable at room temperature.

Immersion scanning system for fabricating porous silicon films

A system for making porous silicon on blank and patterned Si substrates by 'immersion scanning', particularly suitable for fabricating light-emitting Si devices and utilizing an open electolytic cell having a cathode and an opposing anode consisting of a Si substrate on which the porous silicon is to be formed, both disposed, with their opposing surfaces in parallel, in an aqueous HF solution electrolyte contained in the cell. The substrate anode is mounted to be movable relative to the electrolyte so as to be mechanically cycled or scanned in and out of the electrolyte at a programmable rate during anodization. The uniformity, thickness and porosity of the resulting anodized layer on the substrate are determined by the scanning speed, number of cycles, current density, and HF-based electrolyte parameters of the system, and the Si substrate resistivity, conductivity type, and crystal orientation. The light-emitting silicon devices produced incorporate porous silicon layers and are operable at room temperature.

Apparatus for producing porous silicon on a substrate

The subject invention provides a silicon membrane material made from silicon that is epitaxially deposited at low temperatures greater than or equal to 500.degree. C. and doped with controlled amounts of boron and germanium. A silicon membrane structure is provided and made by one or more layers of ultra thin epitaxially deposited silicon layers that are precisely controlled in both thickness and composition. At least one of the layers is doped with boron in a concentration range greater than 2.times.10.sup.20 atoms of boron per cubic centimeter of silicon, or with germanium in a concentration range greater than 5.times.10.sup.20 atoms of germanium per cubic centimeter of silicon, or with a combination of boron and germanium in these concentration ranges. A silicon membrane fabrication process is also provided which requires no additional masking film to protect the membrane surface during KOH etching of the bulk silicon substrate.

Epitaxial silicon membranes

The present invention is directed to a method for forming a self-aligned epitaxial base transistor in a double polysilicon type process using non-selective low temperature epitaxy (LTE) to form the base layer. The present invention utilizes a thin very heavily doped LTE layer that is both a conductive etch stop and a diffusion source for doping the extrinsic base of the transistor. The deposition of the non-selective LTE base layer is followed immediately by the deposition of the conductive etch stop layer. A layer of undoped polycrystalline semiconductor is deposited on the conductive etch stop layer and subsequently ion implanted. Oxide and nitride insulating layers are deposited and the structure is patterned using a highly directional reactive ion etch to form the emitter window leaving a thin layer of the polycrystalline layer. The thin polycrystalline layer is selectively removed in a KOH solution leaving the conductive etch stop layer. The portion of the etch stop layer exposed in the emitter window is selectively removed by oxidation. Thereafter, conventional double polysilicon processing techniques are continued to form the insulator sidewalls and the emitter region in the window. During an annealing drive-in step, the conductive etch stop layer acts as an additional dopant source to the extrinsic base. The etch stop layer provides a conductive contact between the instrinsic base and the extrinsic base of the transistor.

Method for fabricating self-aligned epitaxial base transistor

The method of fabrication of a monolithic silicon membrane structure in which the membrane and its supporting framework are constructed from a single ultra thick body of silicon. The fabrication sequence includes the steps of providing a doped membrane layer on the silicon body, forming an apertured mask on the silicon body, and removal of an unwanted silicon region by mechanical grinding and chemical etching to provide a well opening in the silicon body terminating in the doped membrane.

Monolithic silicon membrane device fabrication process

A mirror array light valve is described comprising a transparent substrate, a plurality of post members arranged in a regular array on said substrate, and a plurality of deflectable square, rectangular, hexagonal or the like light-reflecting elements arranged in a regular array on said post members such that a post member is positioned under a corresponding corner of each element; methods for making the mirror array light valve are also described.

Mirror array light valve

A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.

Method for fabricating transistor structures having very short effective

A family of etchants for polycrystalline silicon based upon an aqueous solution of NR.sub.4 OH, where R is an alkyl group, has a relatively low etching rate enabling the exercise of better control over the delineation of fine structures.

Polycrystalline silicon etching with tetramethylammonium hydroxide

A charge electrode array for use in an ink jet printing apparatus is formed by anisotropic etching of apertures through a single crystal silicon substrate of (110) orientation. Conductive diffusion layers in the walls of and adjacent to the apertures permit a charge to be placed on a jet stream passing through the apertures. Contacts can be formed on the adjacent diffusion layers to provide connection to an externally located charging circuit or the contacts may be omitted when the charging circuit is formed in the substrate itself and connected by diffusion or a metal layer to each adjacent diffusion layer. Jet nozzles and synchronization electrodes are shown incorporated in the charge electrode array to form a monolithic structure capable of performing a plurality of functions. Substrate contacts are also provided for biasing.

Charge electrode array and combination for ink jet printing and method

In an ink jet printing system, a single nozzle or an array of nozzles are etched in a semiconductor material such as silicon. Each nozzle has polygonal or N-sided entrance and exit apertures of different cross-sectional area. Preferably, the nozzle is in the shape of a truncated pyramid with the entrance and exit apertures being substantially square in cross-section. The corners of the apertures and wall interfaces may be rounded to reduce stress concentrations.

Ink jet nozzle

The practice of this disclosure obtains a monolithic structure useful for electrohydrodynamically synchronizing the formation of droplets in a jet stream exiting from a jet nozzle. The monolithic structure is primarily adaptable for ink jet printing. The jet nozzle structure provided by the practice of this disclosure includes a jet nozzle design in a crystalline semiconductor block, e.g., of silicon (Si), germanium (Ge) or gallium arsenide (GaAs), with an electrode structure which is integrally incorporated therewith whereby a variable electric field is established proximate to the orifice of the jet nozzle structure. The electric field electrohydrodynamically perturbs the jet stream emitting from the jet nozzle structure so that formation of drops in the jet stream is controllably achieved, e.g., synchronously when the variable electric field is oscillating with a given periodicity.

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Bronx, NY, United States of America

Ernest Bassous