Honeywell Information Systems Italia

Ermanno Maccario

Alfonso Albani

Claudio Gentili

Ezio Cislaghi

A method of symptom compression involves a symptom compression device receiving binary coded information including bits signifying symptoms present in the course of each operating cycle at selected points in an integrated logical network, microprocessor or the like. The device includes a first register, a second shift register, an EXCLUSIVE OR logic network, and a display. The binary coded information is received on parallel inputs of the first register and applied from parallel outputs of the first register to a set of inputs of the EXCLUSIVE OR network, a second set of inputs which is connected to at least some parallel outputs from the second shift register. A set of outputs from the EXCLUSIVE OR network is connected to parallel inputs of the second shift register. In each cycle, the bits in the second shift register, which accumulate information representative of symptoms, are shifted in one direction and are recirculated. The display is connected to the parallel outputs from the second shift register. In a second embodiment, a third shift register receives the output from the EXCLUSIVE OR network. A multiplexor selectively applies signals from the outputs of the second or third shift register to the second set of inputs. The bits in the third shift register, which also accumulate information as to symptoms, are shifted in the opposite direction. A second display is connected to the outputs of the third shift register.

Method of symptom compression

A symptom compression device receives binary coded information including bits signifying symptoms present in the course of each operating cycle at selected points in an integrated logical network, microprocessor or the like. The device includes a first register, a second shift register, an EXCLUSIVE OR logic network, and a display. The binary coded information is received on parallel inputs of the first register and applied from parallel outputs of the first register to a set of inputs of the EXCLUSIVE OR network, a second set of inputs which is connected to at least some parallel outputs from the second shift register. A set of outputs from the EXCLUSIVE OR network is connected to parallel inputs of the second shift register. In each cycle, the bits in the second shift register, which accumulate information representative of symptoms, are shifted in one direction and are recirculated. The display is connected to the parallel outputs from the second shift register. In a second embodiment, a third shift register receives the output from the EXCLUSIVE OR network. A multiplexor selectively applies signals from the outputs of the second or third shift register to the second set of inputs. The bits in the third shift register, which also accumulate information as to symptoms, are shifted in the opposite direction. A second display is connected to the outputs of the third shift register.

Symptom compression device

A semiconductor memory includes means for separating the causes of error affecting the addressing and recording of information bits from those affecting check, or parity, bits. The recording words comprise 16 information bits, and are divided into two 'bytes', of eight bits each. Each byte is provided with its own check bit; and two half-words of nine bits are recorded at the same address. Each submodule of the memory comprises two printed-circuit cards. The first card supports the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card supports the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded. Since an error cause affecting the control or the addressing circuits mounted on a card does not affect the recording and the addressing circuits of the second card, the recording or addressing of the information bits on one card will differ from the recording and addressing of the related check bit on the other card. Both bytes may be written or read out separately; and the writing or the reading-out signals of the information bits are independent from the writing or reading-out signal of the related check bits for both cards.

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Pregnana Milanese, Italy

Ermanno Maccario