Texas Instruments Corporation

Erkan Bilhan

Venkateswar Reddy Kowkutla

Chunhua Hu

Sumant Dinkar Kale

Francisco A Cano

Haydar Bilhan

Feng Ying

Venkateswara Reddy Pothireddy

Amritpal Singh Mundra

Gonggui Xu

Ramesh Chandrasekaran

Jason Meiners

James E Nave

Lieyi Fang

Rajitha Padakanti

A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

Stress reduction on stacked transistor circuits

A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.

Adaptive voltage scaling system for out of context functional safety SoC

A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.

On chip power on reset with integrated supervisory functions for a functional safety system

A financial transaction system includes sensors, a tamper detection module, and circuitry configurable to control which sensors are used, and the circuitry is configurable after the tamper detection module has been manufactured.

Tamper detection

The optimal operating voltage of a complex SoC may be influenced by process variations. The operating voltages may be dynamically adjusted for optimal performance. These adjustments require a dynamic reconfiguration of the voltage monitoring thresholds in the power on reset circuitry of the SoC.

A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

Dual function analog or digital input/output buffer

A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.

On chip redundant system reset for out of context functional safety SoC

This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and analog circuits. A second, lower power supply powers digital circuits and memory. A first voltage monitor circuit powered by said first power supply generates a first output signal when the first power supply is below an operational limit high level. A second voltage monitor circuit powered by said first power supply indicates when the second power supply is above an operational high limit level. A power switch is controlled by the first voltage monitor circuit. This power switch connects the second power supply and second load when closed and isolates them when open. Thus the memory cannot be accessed when the I/O and analog power supply is out of specification.

Sourcing and securing dual supply rails of tamper protected battery backed domain

An apparatus, system and method for clamping a video signal input to a coupling capacitor () for providing a clamping voltage. A charging current is applied to the capacitor () via an amplifier () having a first input () coupled with the capacitor output and a second input () coupled to a reference potential, the amplifier () is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Clamping circuit for video signals

A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit () includes a clamping capacitor () that couples to an automatic clamping circuit portion () to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (V) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion () connects to the customizable clamping circuit portion () to clamp any portion of the video input signal to a second predetermined reference voltage (V) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer () connects between the customizable clamping circuit portion and the output node of the clamping circuit.

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Dallas, TX, United States of America

Erkan Bilhan