International Business Machines Corporation

Erin C Jones

Kevin K Chan

Arne Watson Ballantine

Paul Michael Solomon

James William Adkisson

Jed Hickory Rankin

Paul David Agnello

Rama Divakaruni

Leathen Shi

Kathryn Wilder Guarini

Bruce Bennett Doris

Edward J Nowak

Omer H Dokumaci

Meikei Ieong

Ramachandra Divakaruni

Hussein Ibrahim Hanafi

Atul Champaklal Ajmera

Suryanarayan G Hegde

Dominic Joseph Schepis

Jeffrey Bowman Johnson

Hon-Sum Philip Wong

Fenton Read McFeely

Sandip Tiwari

Diane Catherine Boyd

Christopher Peter D'Emic

John Jacob Yurkas

Robert J Miller

Dinkar Virendra Singh

Hon-Sum Phillip Wong

Antonio F Saavedra, Jr

Philip Joseph Oldiges

Cheruvu Suryanarayana Murthy

Suryanararyan G Hegde

Rober J Miller

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Self-aligned planar double-gate transistor structure

A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.

Polycrystalline SiGe Junctions for advanced devices

Described is a wet chemical surface treatment involving NHOH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO) at low temperatures (less than or equal to 400&#xb0; C.). Surface energies as high as &#x2dc;4835&#xb1;675 mJ/mof the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000&#xb0; C.). Void free bonding interfaces with excellent yield and surface energies of &#x2dc;2500 mJ/mhave also be achieved herein.

Low temperature fusion bonding with high surface energy using a wet chemical treatment

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Polycrystalline SiGe junctions for advanced devices

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Method of fabricating semiconductor side wall fin

A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

Self-aligned planar double-gate process by self-aligned oxidation

A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

SOI wafers with 30-100 &#x212b; buried oxide (BOX) created by wafer bonding using 30-100 &#x212b; thin oxide as bonding layer

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Double gate trench transistor

SOI wafers with 30-100 &angst; buried oxide (BOX) created by wafer bonding using 30-100 &angst; thin oxide as bonding layer

The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

Self-aligned planar double-gate process by amorphization

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Erin C Jones