Intel Corporation

Altera Corporation

Eriko Nurvitadhi

Balaji Vembu

Kamal Sinha

Rajkishore Barik

Nicolas C Galoppo Von Borries

Tsung-Han Lin

Altug Koker

Abhishek R Appu

Joydeep Ray

Xiaoming Chen

Sara S Baghsorkhi

Nadathur Rajagopalan Satish

Farshad Akhbari

Narayan Srinivasa

Anbang Yao

Feng Chen

Justin E Gottschlich

Dukhwan Kim

Tatiana Shpeisman

Ping Tak Tang

Vasanth Ranganathan

Sanjeev S Jahagirdar

Michael S Strickland

Elmoustapha Ould-Ahmed-Vall

Deborah T Marr

Prasoonkumar Surti

Ben J Ashbaugh

Jeremy Bottleson

Linda L Hurd

Kevin Nealis

Travis T Schluessler

Devan Burke

Subramaniam M Maiyuran

Karthik Vaidyanathan

Adam T Lake

John H Feit

Jeffery S Boles

Wenyin Fu

Josh B Mastronarde

Sanu K Mathew

Mark A Anders

Himanshu Kaul

Liwei Ma

John Charles Weast

Chandrasekaran Sakthivel

Jeffrey J Cook

Asit K Mishra

Ravi Prakash Gutala

Scott J Weber

Amit Bleiweiss

Aravind Raghavendra Dasu

Jonathan D Pearce

David B Sheffield

Dhawal Srivastava

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Jesus Corbal

Rajesh M Sankaran

Edward Thomas Grochowski

Mahesh A Iyer

Koichi Yamada

Thomas D Fletcher

Joseph Nuzman

Stephen R Van Doren

Lokpraveen B Mosur

Paul Caprioli

Dennis Ryan Bradford

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Richard J Greco

Dwight P Manley

Tracy Garrett Drysdale

Srinivas Sridharan

Barath Lakshmanan

Dheevatsa Mudigere

Srikanth T Srinivasan

Mike B Macpherson

Martin Langhammer

Rajesh Poornachandran

Wei W Wang

Ankur N Shah

Ravishankar Iyer

Gregg William Baeckler

Sean R Atsatt

Tomer Bar-On

Abhishek Venkatesh

Wei D Wang

Mike MacPherson

Jonathan Kennedy

John G Gierach

Alaa R Alameldeen

James Loran Ball

Nilesh K Jain

Oguz Hasan Elibol

Davor Capalija

Andrew Ling

Tomasz Czajkowski

Tony Lee Werner

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

Compute optimizations for neural networks

An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Machine learning accelerator mechanism

An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data and customizable circuitry to provide custom functions.

Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanism

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.

Supply voltage control systems and methods for integrated circuits

A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

Circuit systems and methods for reducing power supply voltage droop

The present disclosure relates to an integrated circuit device that includes a plurality of vector registers configurable to store a plurality of vectors and switch circuitry communicatively coupled to the plurality of vector registers. The switch circuitry is configurable to route a portion of the plurality of vectors. Additionally, the integrated circuit device includes a plurality of vector processing units communicatively coupled to the switch circuitry. The plurality of vector processing units is configurable to receive the portion of the plurality of vectors, perform one or more operations involving the portion of the plurality of vector inputs, and output a second plurality of vectors generated by performing the one or more operations.

Vector processor architectures

A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

Voltage regulator circuit systems and methods

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Instructions and logic to perform floating point and integer operations for machine learning

An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

Compute-in-memory systems and methods

A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Efficient thread group scheduling

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Methods, apparatus, systems, and articles of manufacture are disclosed to optimize resources in edge networks. An example apparatus includes agent managing circuitry to invoke an exploration agent to identify platform resource devices, select a first one of the identified platform resource devices, and generate first optimization metrics for the workload corresponding to the first one of the identified platform resource devices, the first optimization metrics corresponding to a first path. The example agent is to further select a second one of the identified platform resource devices, generate second optimization metrics for the workload corresponding to the second one of the identified platform resource devices, the second optimization metrics corresponding to a second path. The example apparatus also includes benchmark managing circuitry to embed second semantic information to the workload, the second semantic information including optimized graph information and platform structure information corresponding to the second one of the identified platform resource devices, and reconfiguration managing circuitry to select the first path or the second path during runtime based on (a) service level agreement (SLA) information and (b) utilization information corresponding to the first and second identified platform resource devices.

Methods, systems, articles of manufacture and apparatus to optimize resources in edge networks

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

Machine learning sparse computation mechanism

Growing community of inventors

Hillsboro, OR, United States of America

Eriko Nurvitadhi