Texas Instruments Corporation

National Semiconductor Corporation

Erika Lynn Mazotti

William David French

Dok Won Lee

Ricky A Jackson

Sudtida Lavangkul

Anuraag Mohan

Wai Lee

Thomas Dyer Bonifield

Yuri Mirgorodski

Neil Gibson

Keith Eric Sanborn

Steve Edward Harrell

Byron J R Shulver

Peter J Hopper

Vladislav Vashchenko

Mark R Visokay

Alexei Sadovnikov

Keith Ryan Green

Richard Wendell Foote, Jr

Punit Bhola

Richard Wendell Foote

An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

Resistor with exponential-weighted trim

A microelectronic device has a Hall sensor that includes a Hall plate in a semiconductor material. The Hall sensor includes contact regions in the semiconductor material, contacting the Hall plate. The Hall sensor includes an isolation structure with a dielectric material contacting the semiconductor material, on at least two opposite sides of each of the contact regions. The isolation structure is laterally separated from the contact regions by gaps. The Hall sensor further includes a conductive spacer over the gaps, the conductive spacer being separated from the semiconductor material by an insulating layer.

Hall sensor with dielectric isolation and p-n junction isolation

An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

Methods and apparatus for scribe street probe pads with reduced die chipping during wafer dicing

Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.

Trimmable silicon-based thermistor with reduced stress dependence

Methods and apparatus for scribe street pads with reduced die chipping during wafer dicing

An integrated fluxgate device has a magnetic core disposed over a semiconductor substrate. A first winding is disposed in a first metallization level above and a second metallization level below the magnetic core, and is configured to generate a first magnetic field in the magnetic core. A second winding is disposed in the first and second metallization levels and is configured to generate a second magnetic field in the magnetic core. A third winding is disposed in the first and second metallization levels and is configured to sense a magnetic field in the magnetic core that is the net of the first and second magnetic fields.

Highly sensitive, low power fluxgate magnetic sensor integrated onto semiconductor process technologies

Some embodiments are directed to an anisotropic magneto-resistive (AMR) angle sensor. The sensor comprises a first Wheatstone bridge comprising a first serpentine resistor, a second serpentine resistor, a third serpentine resistor, and a fourth serpentine resistor. The sensor also comprises a second Wheatstone bridge comprising a fifth serpentine resistor, a sixth serpentine resistor, a seventh serpentine resistor, and an eighth serpentine resistor. The serpentine resistors comprise anisotropic magneto-resistive material that changes resistance in response to a change in an applied magnetic field. The sensor also includes a surrounding of anisotropic magneto-resistive material disposed in substantially a same plane as the serpentine resistors, enclosing the serpentine resistors, and electrically isolated from the serpentine resistors. The first Wheatstone bridge, the second Wheatstone bridge, and the surrounding of anisotropic magneto-resistive material are part of a sensor die.

Anisotropic magneto-resistive (AMR) angle sensor

An integrated fluxgate device has a magnetic core on a control circuit. The magnetic core has a volume and internal structure sufficient to have low magnetic noise and low non-linearity. A stress control structure is disposed proximate to the magnetic core. An excitation winding, a sense winding and a compensation winding are disposed around the magnetic core. An excitation circuit disposed in the control circuit is coupled to the excitation winding, configured to provide current at high frequency to the excitation winding sufficient to generate a saturating magnetic field in the magnetic core during each cycle at the high frequency. An isolation structure is disposed between the magnetic core and the windings, sufficient to enable operation of the excitation winding and the sense winding at the high frequency at low power.

Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor substrate. A scribe region overlying the semiconductor substrate and a periphery of the integrated circuit includes a crack arrest structure and a scribe seal. The crack arrest structure provides first vertical conductor structure that surrounds the periphery of the integrated circuit. The scribe seal is spaced from and surrounded by the crack arrest structure and provides a second vertical conductor structure. The scribe seal includes first and second vias spaced from each other and connected to one of the conductor layers. The first via is a trench via and the second via is a stitch via, with the second via being located closer to the crack arrest structure than the first via.

Crack propagation prevention and enhanced particle removal in scribe line seals of semiconductor devices

An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.

Fluxgate device with low fluxgate noise

A method of fabricating fluxgate devices to measure the magnetic field in two orthogonal, in plane directions, by using a composite-anisotropic magnetic core structure.

Integrated dual axis fluxgate sensor using double deposition of magnetic material

An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated circuit dies arranged in rows and columns and spaced apart by the scribe streets. Each integrated circuit die includes plurality of active areas; a plurality of insulator layers overlying the active areas; a plurality of conductor layers interspersed with and separated by ones of the insulator layers; and a passivation layer overlying a top portion of the uppermost one of the conductor layers. A scribe seal in a scribe region surrounds the periphery of the integrated circuit dies, the scribe seal covered by the passivation layer; and a crack arrest structure is located surrounding and spaced from the scribe seal, and including an opening in the passivation layer that extends to and exposes the upper surface of the crack arrest structure. Methods are disclosed.

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San Martin, CA, United States of America

Erika Lynn Mazotti