Advanced Micro Devices Corporation

Spansion Llc.

Other

Cypress Semiconductor Corporation

Advanced Micro Devices, Inc. and Spansion LLC

Erik Wilson

Lu You

Minh Quoc Tran

Alexander H Nickel

Hieu T Pham

Minh Van Ngo

Robert A Huertas

Hirokazu Tokuno

William S Brennan

Zheng Wang

Connie P Wang

Inkuk Kang

Wen Yu

Minh-Van Ngo

Pei-Yuan Gao

Allen Lewis Evans

Robert J Chiu

Amir Hossein Jafarpour

Sung Jin Kim

An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.

Ruthenium interconnect with high aspect ratio and method of fabrication thereof

During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 &#x212b; to about 500 &#x212b;, curing after deposition, as by UV radiation or by heating at a temperature of about 400&#xb0; C. to about 1000&#xb0; C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Gap-filling with uniform properties

A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% Nwith less than 10% H, performing planarization, performing in-situ low-H NHplasma treatment and low Si&#x2014;H SiN etch stop layer deposition, and performing remaining back end processing.

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Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an Natmosphere containing low Hor no H, and at temperatures less than 200&#xb0; C., e.g., 100&#xb0; C. to 150&#xb0; C.

Cu annealing for improved data retention in flash memory devices

Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si&#x2014;H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si&#x2014;H bonds on the first silicon nitride layer for reduced charge loss.

Semiconductor devices with copper interconnects and composite silicon nitride capping layers

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Santa Clara, CA, United States of America

Erik Wilson