Kepler Computing Inc.

Erik Unterborn

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Tanay Gosavi

Noriyuki Sato

Debo Olaosebikan

Pramod Kolar

Mustansir Yunus Mukadam

Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Non-linear polar material based multi-capacitor high density bit-cell

Growing community of inventors

Cary, NC, United States of America

Erik Unterborn