International Business Machines Corporation

Erik S Unterborn

James David Strom

Grant Paul Kesselring

Dureseti Chidambarrao

Karl L Ladin

John Michael Borkenhagen

Michael Sperling

David Michael Friend

Matthew S Angyal

Joel T Ficke

Ann Chen Wu

Noah D Zamdmer

Varadarajan Vidya

A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.

Device mismatch mitigation for medium range and beyond distances

A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.

Higher yielding improved matching reference circuit especially applicable for high speed mixed signal applications and phase locked loops and charge pumps

A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.

Multi-mode design and operation for transistor mismatch immunity

A semiconductor chip having a P&#x2212; substrate and an N+ epitaxial layer grown on the P&#x2212; substrate is shown. A P&#x2212; circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.

Moat construction to reduce noise coupling to a quiet supply

Systems and computer program products for layout device matching driven by a schematic editor. Exemplary embodiments include identifying a master device in a circuit layout having at least transistors, the master device having property values including at least one of topology, name and device-type, identifying a cloned device linked to the master device, automatically propagating the property values to the cloned device, making changes to a design layout of the master device, including a change to the properties, and automatically propagating the changes to the design layout and the change to the properties of the master device to the cloned device.

Methods, systems and computer program products for layout device matching driven by a schematic editor

A method for designing shielding in integrated circuits, the method comprising, receiving a first input designating a first net segment profile on a first level in an integrated circuit for shielding, determining whether the designated first net segment profile is in electrical communication with other net segment profiles, determining whether the net segment profiles are located in a different level than the first net segment profile, defining a first shielding profile corresponding to the net segment profiles on the first level, defining a second shielding profile corresponding to the net segment profiles on the second level, determining and removing segments of the first shielding profile and the second shielding profile contact features of the integrated circuit, determining and removing segments of the first shielding profile and the second shielding profile are non-continuous, defining vias at the intersections of first shielding profile and the second shielding profile.

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Pine Island, MN, United States of America

Erik S Unterborn