Telefonaktiebolaget Lm Ericsson (publ)

Erik O Abefelt

Karl A Bjenne

Peter Carl Lundh

Sture G Roos

Lars-Goran Petersen

Carl P Lundh

Arto Juhani Nummelin

A method and apparatus for testing for correct connection together of circuit elements in a circuit formed of a plurality of redundant circuit portions. A coded signal is generated at a first circuit element and transmitted upon a signal path believed to connect the first circuit element with a second circuit element. If the coded signal is detected at the second circuit element, the correct connection of the first circuit element together with the second circuit element is verified. Because a coded signal is generated, the correct connection between the circuit elements can be verified even when the signal path connecting the first and second circuit elements is formed of an optical, or other non-electrical, coupler.

Testing method and apparatus for verifying correct connection of curcuit

A fast operating, combined packet and circuit switch. The switch includes a number of units which are distributed locally and which are mutually connected by means of physical links. In a packet-switched network, which is comprised of packet handlers and the links, each connected unit affects at least one control-time-slot. In this way, each unit is able to operate the circuit switch so as, for instance, to establish and release circuit-switched connections, in response to control commands transmitted on the packet-switched network. As a result of the packet switch, the whole of the switch can be configured at a cold start and during operation, therewith satisfying the individual bandwidth requirement of each connected unit.

Fast operating program controlled digital uniswitch

The invention relates to a multiplexer for a digital switch, arranged to be included in a switch network whose data flow is organized in frames containing a number of time slots, said time slots including data time slots, which shall be directed through the switch from first to second sets of terminal units, such as subscriber connections, trunk connections, processors, etc. The multiplexer is controlled by a processor for controllable multiplexing, i.e., mapping of a number of transmission links from each of a corresponding number of the terminal units of said first set to a transmission link leading to the switch, as well as of a transmission link leading from the switch to a number of transmission links leading to each of a corresponding number of terminal units of said second set. The mapping is performed on the data time slots. All data time slots arriving from the terminal units of said first set are to be sent forward via a first buffer to the switch in an order which is determined by a first control memory for the mapping, and all data time slots arriving from the switch are to be sent forward via a second buffer toward the terminal units of said second set in an order which is determined by a second control memory for the mapping. The buffers are implemented as fifos, one for each of the links from and to the terminal units.

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Vallingby, Sweden

Erik O Abefelt