International Business Machines Corporation

Erik Mattias Dahlstrom

Qizhi Liu

Renata A Camillo-Castillo

Robert J Gauthier, Jr

Yun Shi

Richard A Phelps

Ephrem G Gebreselasie

Peter B Gray

Kevin K Chan

Jed Hickory Rankin

Alvin Jose Joseph

Robert Mark Rassel

David Louis Harame

Andreas Daniel Stricker

David Charles Sheridan

A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage

Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

Silicon controlled rectifier with stress-enhanced adjustable trigger voltage

Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.

Bipolar junction transistor with a self-aligned emitter and base

Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

Heterojunction bipolar transistors with reduced base resistance

Methods of fabricating a bipolar junction transistor with a self-aligned emitter and base

Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance

Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

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Burlington, VT, United States of America

Erik Mattias Dahlstrom