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Erik Lind

Lars-Erik Wernersson

Lars Samuelson

Jonas Ohlsson

Tomas Bryllert

Truls Lowgren

Claes Thelander

Truls Löwgren

Mikael Egard

Johannes Svensson

Martin Berg

Karl-Magnus Persson

Mikeal Bjork

Anil Dey

Mikael BJÖRK

A method for fabrication of vertical nanowire MOSFETs is considered using a gate-last process. The top ohmic electrode is first fabricated and may be used as a mask to form a gate recess using etching techniques. The gate is thereafter formed allowing a large degree in access resistance reduction.

Method for vertical gate-last process

A radial nanowire Esaki diode device includes a semiconductor core of a first conductivity type and a semiconductor shell of a second conductivity type different from the first conductivity type. The device may be a TFET or a solar cell.

Radial nanowire Esaki diode devices and methods

According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (), providing a mask () on the channel layer, epitaxially growing a contact layer () in contact with the channel layer, epitaxially growing a support layer () on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor () in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.

Process for manufacturing a semiconductor device and an intermediate product for the manufacture of a semiconductor device

The present invention relates to providing layers of different thickness on vertical and horizontal surfaces () of a vertical semiconductor device (). In particular the invention relates to gate electrodes and the formation of precision layers () in semiconductor structures comprising a substrate () and an elongated structure () essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device () is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Method of producing precision vertical and horizontal layers in a vertical semiconductor structure

The present invention relates to providing layers of different thickness on vertical and horizontal surfaces () of a vertical semiconductor device (). In particular the invention relates to gate electrodes and the formation of precision layers () in semiconductor structures comprising a substrate () and an elongated structure () essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device () is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

The present invention relates to nanoscaled electronic devices with a vertical nanowire as a functional part. Contacts are arranged on the nanowire at different parts of the nanowire, for example drain and source contacts. In connection to the nanowire contacts are external electrodes, that connect at different levels, as seen from the substrate, of the device. The external electrodes are elongated, and typically and preferably stripe-like. According to the invention a first external electrode, or contacts, associated with contact(s) at a first part of the nanowire, and a second external electrode, associated with contact(s) at a second part of the nanowire are arranged in a cross-bar configuration. The cross-bar configuration minimizes the overlay of the external electrodes, hence, parasitic capacitances and current leakage can be reduced, and the performance of the device improved.

Semiconductor nanowire vertical device architecture

A nanowire wrap-gate transistor is realized in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

Semiconductor nanowire transistor

The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

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Lund, Sweden

Erik Lind