Atmel Corporation

Atmel Corportation

Erik Knutsen Renno

Oyvind Strom

Ronny Pedersen

Andreas Due Engh-Halstvedt

Frode Milch Pedersen

Morten Werner Lund

Are Arseth

Havard Skinnemoen

Kristian Monsen

Øyvind Strøm

Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction.

Method for performing a return operation in parallel with setting status flags based on a return value register test

Apparatus, systems, and methods may operate to receive from a requesting device, at a memory device, a request to access a memory domain associated with the memory device, and to deny, by the memory device, the request if the memory domain comprises any part of a secure domain, and the requesting device has not asserted a secure transfer indication. Additional operations may include granting the request if the memory domain comprises some part of the secure domain and the requesting device has asserted the secure transfer signal, or if the memory domain comprises only a non-secure domain. Additional apparatus, systems, and methods are disclosed.

Secure information processing

A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.

Packed add-subtract operation in a microprocessor

The present disclosure includes, among other things, methods, systems, program products, and devices for providing access to memory in a system with memory protection. A request is received from a processor for a memory access at a first memory location. A second memory location is determined. The second memory location is associated with the first memory location and is protected from access by the processor. The requested memory access is performed at the second memory location.

Accessing memory in a system with memory protection

A method can include receiving a signal associated with an attempted access to data that is stored at a specific location in memory; obtaining a selection value that selects which memory protection register of multiple alternative memory protection registers is to provide a memory protection attribute for the specific location in memory; obtaining, from the selected memory protection register, a memory protection attribute; and controlling access to the specific location in memory based on the obtained memory protection attribute.

Configurable memory protection

An apparatus for performing multiply-accumulate operations in a microprocessor comprising operand input registers for receiving data to be operated on an adder and a multiplier for performing operations on the data, a result output port for presenting results to the microprocessor, a multiplexer for storing results, an accumulator cache for storing an accumulator value internal to the apparatus, and control circuitry for controlling the operation of the apparatus.

Apparatus and method for performing efficient multiply-accumulate operations in microprocessors

An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon execution of a supervisor return instruction. The supervisor call instruction can be called from all contexts.

Microprocessor instruction that allows system routine calls and returns from all contexts

An adaptation of the sum-of-absolute-differences (SAD) calculation is implemented by modifying existing circuitry in a microprocessor. The adaptation yields a reduction of over 30% for a current SAD calculation. The adaptation includes a first and second operand register, each storing respectively a first and second set of 2's complement binary data, an arithmetic logic unit (ALU), and a destination register. An add/subtract enable input on the ALU receives a most significant bit (MSB) of the second set of binary data. The ALU adds the first and second data sets if the MSB is a '0' and subtracts the second data set from the first data set if the MSB is a '1.' The add/subtract enable input has the effect of taking the absolute value of the second data set without having to first perform an absolute value determination, thus eliminating processing steps.

System for increasing the speed of a sum-of-absolute-differences operation

An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition.

Method and apparatus for formatting numbers in microprocessors

Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions for a program, where the software breakpoint replaces at least one of the instructions. The system may also include an instruction replacement register separate from the program memory that is configured to receive the replaced instruction from any of the processor and an external debugger. The system may further include a control component that controls whether the processor fetches a next instruction for execution from the program memory or from the instruction replacement register.

Debugging system and method for use with software breakpoint

A combined native (RISC or CISC) microprocessor and stack (Java&#x2122;) machine are constructed so that Java&#x2122; VM instructions can be executed in hardware. Most Java&#x2122; instructions are executed directly, while more complex Java&#x2122; instructions, such as those manipulating Java&#x2122; objects, are executed as native microcode. In order for native microcode instructions to access the Java&#x2122; operand stack, a Java&#x2122; operand stack pointer points to the register file location that is the current top of the stack, while a remap bit in the status register indicates that registers specified in native instructions are remapped as the maximum Java&#x2122; operand stack pointer value minus the present value of the Java&#x2122; operand stack pointer.

Microprocessor access of operand stack as a register file using native instructions

A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.

Growing community of inventors

Trondheim, Norway

Erik Knutsen Renno