Sun Microsystems, Inc.

Erik E Hagersten

Mark Donald Hill

Paul N Loewenstein

Ashok Singhal

David Allen Wood

Christopher J Jackson

Monica C Wong-Chan

Robert C Zak, Jr

Aleksandr Guzovskiy

William A Nesheim

Bjorn O Liencres

Nalini Agarwal

David J Broniarczyk

Hien H Nguyen

Håkan E Zeffer

Frederick M Cerauskis

Jeff Price

Gerald Cheung

Robert Cypher

Shailender Chaudhry

Anders Landin

Zoran Radovic

Shaw-Wen Yang

John R Catenzaro

In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

Value-based memory coherence support

In one embodiment, a node for a multi-node computer system comprises a coherence directory configured to store coherence states for coherence units in a local memory of the node and a coherence controller configured to receive a coherence request for a requested coherence unit. The requested coherence unit is included in a memory region that includes at least two coherence units, and the coherence controller is configured to read coherence states corresponding to two or more coherence units from the coherence directory responsive to the coherence request. The two or more coherence units are included in a previously-accessed memory region, and the coherence controller is configured to provide the requested coherence unit with a predicted coherence state responsive to the coherence states in the previously accessed memory region.

Speculative directory lookup for sharing classification

A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node.

Hierarchical SMP computer system

A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation. The address identifies the destination coherency unit within the local node, and a translation of the address to a global address identifies the source coherency unit. Subsequent to completion of the copy operation, the destination coherency unit may be accessed in the local node.

Multiprocessing system configured to perform efficient block copy operations

A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to local memory space of a node such that accesses to the data may be performed locally rather than globally. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, multiple pages of the address space are mapped to an entry in a translation table. To decrease the probability that an entry is not available for a page, the translation table may be implemented as a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

Skewed finite hashing function

A multiprocessing computer system employs local and global address spaces and multiple access modes. A portion of the global memory of the multiprocessing computer system is allocated to each node, called local memory space. Two logical address spaces are mapped to the local memory of each node. A coherent memory replication (CMR) address space stores shadow pages of data from remote nodes and a local address space stores local data. A bit within a local physical address identifies whether data is a shadow page, which is stored in CMR space, or local data, which is stored in local address space. When a transaction requiring a coherency operation is performed, the CMR bit indicates whether a local physical address to global address translation is required. In one embodiment, if the CMR bit is clear, the local physical address is the same as the global address and the local physical address is used for the coherency operation. Alternatively, if the CMR bit is set, the local physical address is translated to a global address during the coherency operation.

Selective address translation in coherent memory replication

A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

Repeater for use in a shared memory computing system

A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the first waiting contender, and the other waiting contenders. The first waiting contender is made probabilistically more likely to obtain the lock by having it spin faster than the other waiting contenders. Because the other waiting contenders spin more slowly, the first waiting contender is more likely to be able to observe the free lock and acquire it before the other waiting contenders notice that it is free. The first of the other waiting contenders that determines that the previous first waiting contender has acquired the lock is promoted to be the new first waiting contender and begins spinning fast. Because only the first waiting contender is spinning fast on the lock, it is probable that only the first waiting contender will attempt to acquire the lock when it becomes available.

System and method for accessing a shared computer resource using a lock featuring different spin speeds corresponding to multiple states

A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block. There is also included the step of sending, if the home node does not have a first valid copy of the memory block, a request from the home node to a second plurality of nodes in the computer network to request a second node in the computer network to send the first valid copy of the memory block to the first node. The second plurality of nodes represents the first plurality of nodes excepting the first node and the home node. The first valid copy of the memory block represents a valid copy that is capable of servicing the first memory access request.

Methods and apparatus for a directory-less memory access protocol in a distributed shared memory computer system

A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.

Hybrid memory access protocol in a distributed shared memory computer system

A multiprocessing system includes a plurality of nodes interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote node's memory. A cluster protection mechanism is employed within a system interface of the remote node. The system interface, which is coupled between the global interconnect network and a local bus of the remote node, includes a memory management unit, referred to as a cluster MMU, including a plurality of entries which are selectable on a page basis. Depending upon the particular address of a received global transaction, an entry within the memory management unit is retrieved. The entry includes various fields which may be used to protect against accesses by unauthorized nodes, and to specify the local physical address to be conveyed upon the local bus. A field of the entry is further provided to control the type of operation performed upon the local bus by the system interface in response to the global interface. In one implementation, several different command types may be specified by the particular entry of the memory management unit, including normal memory operations, atomic test and set operations, I/O operations and interrupt operations, among others. Additional control registers may further be provided within the system interface to specify further protection parameters and/or functionality. For example, in one embodiment, a control register is provided within the system interface to store values indicative of the other nodes of the system which are allowed access to this node's local memory.

Multiprocessing computer system employing a cluster protection mechanism

In one embodiment, a multiprocessing computer system includes a plurality of nodes. The plurality of nodes may be interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote nodes memory. In the event of an error, an error status register of a system interface of the launching cluster node is set to indicate the occurrence of an error. The error may be the result of an access violation, or the result of a time-out occurrence in either the remote node or the initiating node. Various other errors may alternatively be reported. The system interface advantageously includes a plurality of error status registers, with a separate error status register provided for each processor included in the node. A process running on any of the processors of the node reads an error by issuing a transaction to a unique address, wherein the unique address is independent of the processor upon which the process is running. The unique address as well as the transaction ID indicative of the processor which is attempting to read an error status are used by the system interface to determine which of the plurality of error status registers to access.

Multiprocessing computer system employing a cluster communication error reporting mechanism

A multiprocessing computer system includes a plurality of nodes interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote node's memory. In one specific implementation, the address base of the system is divided into &ldquo;slices&rdquo;. Different slices may correspond to the local memory of differing cluster nodes. The system interface of each node advantageously includes a lookup table which is used to associate selected address regions, or slices, with specific remote nodes for which the slices are local. Accordingly, when a processor within a node initiates a transaction on a local bus, the system interface of that node accesses its lookup table to determine whether that transaction should be conveyed to a remote node, as determined by the corresponding entry of the lookup table for that transaction's address. Otherwise, the transaction is a local transaction and is not conveyed upon the global bus network. More than one system interface may be provided in a particular node. In one particular implementation, a specific slice may have a valid entry in more than one of the node's system interfaces. In that case, the different system interfaces may be initialized to handle a subset of the accesses for that slice. For example, one system interface may handle even address transactions for that slice and the other system interface may handle the odd address transactions for that slice. In this manner, increased bandwidth to one specific node may be advantageously provided. In another specific implementation wherein several system interfaces reside in one node, a specific cluster slice may have a valid lookup table entry in only one of the system interfaces. In this manner, increasing the number of system interfaces may advantageously accommodate increased connectivity for the node with respect to the number of other nodes to which the node may be connected.

Growing community of inventors

Palo Alto, CA, United States of America

Erik E Hagersten