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Erik De Man

Stefan Ingo Meier

Tobias Noll

Matthias Schobinger

Clock generator for CMOS circuits with dynamic registers

Low loss integrated circuit with reduced clock swing

A series of adders (AD.sub.i) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the bit-parallel addition of binary numbers in two's complement with carry-save overflow correction. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, in case the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by the carry bit thereof. The element AD.sub.kn-1 has the same number of transistors as the other adders AD.sub.0 . . . AD.sub.n-2.

Arrangement for bit-parallel addition of binary numbers with carry-save

ECL-compatible input/output circuits in CMOS technology which meet very strict ECL level demands and are as independent as possible of temperature and field effect transistor parameter fluctuations. This is achieved by a control circuit for reference currents of the current mirror circuits. The control circuit is composed of a sensor stage, of a comparator, of a low-pass filter and of a reference current source. Current mirror circuits are also utilized in the driver stages and in the sensor stage.

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Munchen, Germany

Erik De Man