International Business Machines Corporation

Erik Breiland

Charles S Chiu

Prince George

Barry Jay Rubin

Ullrich Richard Pfeiffer

Timothy W Budell

Edward R Pillai

Paul Lee Clouser

Charles K Erdelyi

Brian P Welch

The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

System and method for modeling I/O simultaneous switching noise

A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.

Chip-based prober for high frequency measurements and methods of measuring

The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models particularly related to microelectronic packages. The method discloses creation of equivalent circuits for geometries encountered in a typical chip package, including how to partition the geometry into cells which are less then 1/20 the minimum wavelength (&#x3bb;) in size, and how to handle signal and power supply vias, signal wires, and power planes. The method also instructs how to assign values to each of the inductors, capacitors, resistors, and transmission lines in each equivalent circuit. The method further provides modeling of only those interactions which occur between adjacent cells.

Hierarchical method of power supply noise and signal integrity analysis

A technique for simplifying a structure so that subsequent electrical analysis can be more efficiently performed. The technique includes facility to modify the existing shapes in the structure so that they do not overlap, to determine the allowed movement of each edge of each shape in the structure, to apply a set of factors to each movement that determines how advantageous the movement is with respect to the number of unknowns and the change in geometry and/or electrical parameters of the structure, and to choose and then make the movement associated with the highest factor. The factors are unity based so that the desirability of the move is given by the product of all the factors. The technique includes facility to iterate, calculating the factors and making the movement associated with the greatest factor, until the factor falls below a given threshold. The resulting structure will be similar in electrical characteristics to the original structure, yet require fewer unknowns to analyze.

Growing community of inventors

Colchester, VT, United States of America

Erik Breiland