Texas Instruments Corporation

Apple Inc.

Erick Omar Torres

Harish Venkataraman

Byungchul Jang

Philomena Cleopha Brady

Jay B Fletcher

Gary Franklin Chard

Fabio Gozzini

Timothy Bryan Merkin

Hubert Attah

Hassan Pooya Forghani-Zadeh

Karan Singh Jain

Khaled M Alashmouny

Sunil Bhosekar

Suresh Balasubramanian

Bruce Andrew Doyle

Chad O Lackey

Sharath R Srinivasan

Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.

Clock duty cycle correction

An inductor conducts a first current, which is variable. A first transistor is coupled through the inductor to an output node. The first transistor alternately switches on and off in response to a voltage signal, so that the first current is: enhanced while the first transistor is switched on in response to the voltage signal; and limited while the first transistor is switched off in response to the voltage signal. A second transistor is coupled to the first transistor. The second transistor conducts a second current, which is variable. On/off switching of the second transistor is independent of the voltage signal. Control circuitry senses the second current and adjusts the voltage signal to alternately switch the first transistor on and off in response to: the sensing of the second current; and a voltage of the output node.

Method and circuitry for sensing and controlling a current

USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state.

Circuit and method for interfacing universal serial bus

A circuit includes a current sensor to sense a switching current flowing at input side of a switching DC-DC converter. An output capacitor filters an output voltage at an output side of the switching DC-DC converter. A feed-forward circuit passes a portion of the sensed switching current to a feedback path on the output side of the switching DC-DC converter simulating a changing effective series resistance (ESR) of the output capacitor to facilitate operating stability in the switching DC-DC converter.

Feedforward loop to stabilize current-mode switching converters

An apparatus is disclosed, including a driver circuit, a comparator circuit, and a counter circuit. The driver circuit may be configured to source a current to a load circuit. The comparator circuit may be configured to perform a comparison of a reference voltage to a voltage across the load circuit. The counter circuit may be configured to modify a digital count value based on the comparison. The driver circuit may be further configured to adjust a value of the current using the digital count value.

Digital secondary control loop for voltage converter

A method of decoding a biphase mark coded (BMC) data stream. A BMC encoded signal (BMC signal) including a preamble and data payload is received at a receiver which includes a BMC decoder state machine (state machine). The preamble is processed using the state machine including measuring a total duration spanning at least three transitions to provide a &#x2267;2 UI duration measure, a calculated 0.75 UI duration value (0.75 UI duration value) is generated from the &#x2267;2 UI duration measure, and the 0.75 UI duration value is compared to a programmed UI range. Provided the 0.75 UI duration value is within the programmed UI range data, respective bits are extracted bit-by-bit from the data payload using the 0.75 UI duration value to obtain unencoded data.

Self-learning and self-correcting decoding of BMC encoded signal

A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a power switch(es). Control circuitry includes a voltage sensor sensing Vout and a voltage level generator for generating a first voltage level coupled to the CP stage and a second voltage level coupled to a duty cycle/rate generator block providing an input to an under voltage (UV) monitor coupled between OUT and the control logic. The control circuitry disables the CP when Vout&#x3e;a first Vout level and controls the BC to regulate to a second Vout level&#x3e;the first Vout level. During handoff between CP and BC during power up if Vout drops below a UV threshold, the UV monitor block modifies an input applied to the control logic for increasing charging supplied to the inductor.

Droop reduction circuit for charge pump buck converter

A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

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Allen, TX, United States of America

Erick Omar Torres