Texas Instruments Corporation

Erick D Oakland

Richard D Simpson

Karl M Guttag

Robert J Gove

Christopher Jensen Read

Sydney W Poland

Jeremiah E Golston

Michael C Gill

Nicholas Ing Simmons

Graham M Barr

A double precision rounding unit is employed for both single and double precision rounding. Rounding double precision mantissas employs the double precision rounding unit normally. For rounding single precision mantissas, the single precision mantissa is both left and right justified at the inputs of the double precision rounding unit. The N bits of the single precision number are supplied to a set of N least significant bit inputs of the double precision rounding unit. The N bits of the single precision number are also supplied to a set N of most significant bit inputs of the double precision rounding unit. The central M bits, which are between the set of N least significant bit inputs and the set of N most significant bit inputs are supplied with zeros. The double precision rounding unit is operated normally with the single precision input. A single precision/double precision masking unit at the output of the double precision rounding unit selects the proper bits. In double precision mode, all the output bits of the double precision rounding unit are valid. In single precision mode, only the N most significant outputs of the double precision unit are valid.

Left and right justification of single precision mantissa in a double

A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.

Data processor having capability to perform both floating point

A magnitude comparator employs plural layers of repeated circuits which are scalable to any size. The magnitude comparator indicates whether two multibit inputs are equal, and if not equal indicates if a first multibit input is greater than a second multibit input. A single bit comparator circuit receives a corresponding bit of the two multibit inputs. Each single bit comparator generates an A=B output equal to the exclusive NOR of the two inputs and an A&gt;B output equal to the first input. The magnitude comparator includes at least one two bit comparator circuit disposed in at least one layer. Each two bit comparator circuit includes an A[0]=B[0] input, an A[0]&gt;B[0] input, an A[1]=B[1] input and an A[1]&gt;B[1] input. Each two bit comparator circuit generates an A=B output of an AND of signals received at the A[0]=B[0] and A[1]=B[1] inputs. Each two bit comparator circuit generates an A&gt;B output equal to the A[1]&gt;B[1] input if the A[0]=B[0] input is '1' and equal to the A[0]&gt;B[0] input if the A[0]=B[0] input is '0'.

Floating point exponent compare using repeated two bit compare cell

A controllable width OR gate employs a plurality of controllable OR gate cells. If the maximum width of the data to be ORed is N bits, then N-1 such controllable OR gate cells are needed. Each controllable OR gate cell 100 has four data inputs, OR0, ST0, OR1 and ST1, and a single control input CO. Each controllable OR gate cell has two outputs: ORout and STout. A first OR gate forms the OR of the OR0 and OR1 inputs unconditionally as the ORout output. A second OR gate forms the OR of the OR0 input and the ST1 input. Two pass gates are controlled in the opposite sense via the signal on control input C0 due to an invertor. If C0 is '1', then the output the second OR gate (OR0 OR ST1) is supplied to output STout. If C0 is '0', the ST0 input is supplied to output STout. Layers of the controllable OR gate cell can be used to from a wide controllable width OR gate. Each layer of cells is controlled by a corresponding bit of the control word. The STout of a single cell of a final layer forms the controllable width OR gate output.

Controllable width or gate

A floating point normalization circuit and method decodes the exponent generating a coded multibit output corresponding to the maximum decrease in the exponent within the minimum expressible exponent. This coded multibit output is bit-wise ORed with the mantissa. A left most one circuit detects the bit position of the most significant bit of the logical OR output having a '1'. The mantissa and exponent are them normalized according to this number. The mantissa is left shifted an amount equal to this detected bit position of a most significant bit having a '1'. The exponent is decremented an amount equal to this detected bit position of a most significant bit having a '1'. The exponent decoder generates said coded multibit output in the form of a mantissa equal to the minimum mantissa that can be normalized for the input exponent part of the floating point number. This minimum mantissa is equal to 2.sup.(M+N), where M is the minimum expressible exponent and N is the exponent. In the preferred embodiment, the exponent decoder includes a two to four line decoder for each pair of bits of the exponent part of the floating point number, and an AND gate connected to selected outputs of said two to four line decoders for each bit of said mantissa.

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Zavalla, TX, United States of America

Erick D Oakland