Qualcomm Incorporated

Q, LLC

Erich Plondke

Lucian Codrescu

Mao Zeng

William C Anderson

Muhammad Ahmed

Ajay Anant Ingle

Suresh Kumar Venkumahanti

Christopher E Koob

Charles Joseph Tabony

Eric W Mahurin

Shankar Krithivasan

Sujat Jamil

David J Hoyle

Taylor Simpson

Jonathan Dewitt Wolfe

Thomas Andrew Sartorius

Piyush Chunilal Patel

Rexford Alan Hill

Evandro Carlos Menezes

Remi Jonathan Gurski

Robert Allan Lester

Jiajin Tu

Albert Danysh

Bryan C Bayerdorffer

Swaminathan Balasubramanian

Colin Beaton Verrilli

Chirag Sureshbhai Patel

Phillip M Jones

Paul Bassett

Suhail Jalil

Robert Paul Turner

Dana Michelle Vantrease

Fadi Adel Hamdan

Aaron Douglass Lamb

Xufeng Chen

Billy Brumley

Tijmen Pieter Frederik Blankevoort

Junchen Du

Can Acar

Bo Zhou

Shu Xiao

Kim-Chyan Gan

Muhammad Tauseef Rab

Hitesh Kumar Gupta

Peixin Zhong

Rahul R Toley

Vijaya Kumar Janjanam

Donald Robert Padgett

Pavel Potoplyak

Shane M Mahon

Richard Kuo

Michael R McDonald

Eric Mahurin

An aspect of the disclosure relates to a data processing system, including: an input medium configured to include a first set of blocks of data including a first set of block of compressed data and a first set of metadata, respectively; an output medium configured to include a first set of blocks of decompressed data each having a predetermined number of decompressed elements; and a set of single instruction multiple data (SIMD) processors configured to: access the first set of blocks of data from the input medium, respectively; decompress the first set of blocks of compressed data to generate the first set of blocks of decompressed data based on the first set of metadata, respectively; and provide the first set of blocks of decompressed data to the output medium, respectively.

Single instruction multiple data (SIMD) sparse decompression with variable density

A method for an artificial neural network includes receiving an input. A quantization threshold is determined based on the input, or a characteristic or type of the input. Neural network values, such as weights or activations, of one or more layers of the artificial neural network are quantized according to the quantization threshold. The artificial neural network generates an output based on the quantized neural network values.

Variable quantization for neural networks

Certain aspects of the present disclosure provide techniques for generating execution schedules, comprising receiving a data flow graph for a process, where data flow graph comprises a plurality of nodes and a plurality of edge; generating a topological ordering for the data flow graph based at least in part on memory utilization of the process; generating a first modified topological ordering by inserting, into the topological ordering, one or more new nodes corresponding to memory access based on a predefined memory capacity; allocating units of memory in the memory based on the first modified topological ordering; and generating a second modified topological ordering by rearranging one or more nodes in the first modified topological ordering, where the second modified topological ordering enables increased parallel utilization of a plurality of hardware components.

Memory-bound scheduling

Aspects described herein provide a method of processing data in a machine learning model, including: receiving first domain input data; transforming the first domain input data to second domain input data via a domain transformation function; providing the second domain input data to a first layer of a machine learning model; processing the second domain input data in the first layer of the machine learning model according to a set of layer weights; and outputting second domain output data from the first layer of the machine learning model.

Machine learning with input data domain transformation

A method of constraining data represented in a deep neural network is described. The method includes determining an initial shifting specified to convert a fixed-point input value to a floating-point output value. The method also includes determining an additional shifting specified to constrain a dynamic range during converting of the fixed-point input value to the floating-point output value. The method further includes performing both the initial shifting and the additional shifting together to form a dynamic, range constrained, normalized floating-point output value.

Constraining function approximation hardware integrated with fixed-point to floating-point conversion

A processor includes a vector register configured to load data responsive to a special purpose load instruction. The processor also includes circuitry configured to replicate a selected sub-vector value from the vector register.

System and method of loading and replication of sub-vector values

A method of generating a feature descriptor includes determining a first output histogram of an input by processing a first group of pixels of the input to determine first contributions to bins of the first output histogram. The input image including gradient orientation values and gradient magnitude values of a portion of an image that is in a region of a detected feature. After processing the first group of pixels, the method includes determining a second output histogram of the input by processing a second group of pixels of the input to determine second contributions to bins of the second output histogram.

System and method of feature descriptor processing

An apparatus includes a first processor having a first instruction set and a second processor having a second instruction set that is different than the first instruction set. The apparatus also includes a memory storing at least a portion of an operating system. The operating system is concurrently executable on the first processor and the second processor.

Executing an operating system on processors having different instruction set architectures

A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

System and method of floating point multiply operation processing

Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.

Floating point constant generation instruction

An apparatus includes a processor and a guest operating system. In response to receiving a request to create a task, the guest operating system requests a hypervisor to create a virtual processor to execute the requested task. The virtual processor is schedulable on the processor.

Systems and methods of using a hypervisor to assign virtual processor priority based on task priority and to schedule virtual processors for guest operating systems

A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.

Externally programmable memory management unit

Systems and method of error checking for instructions method of error checking for instructions include an assembler for creating an instruction packet with one or more instructions, determining if a parity of the instruction packet matches a predesignated parity, and if the parity of the instruction packet does not match the predesignated parity, using a bit of the instruction packet to change parity of the instruction packet to match the predesignated parity. The instruction packet with the predesignated parity is stored in a memory, and may eventually be retrieved by a processor for execution. If there is an error in the instruction packet retrieved from the memory, the error is detected based on comparing the parity of the instruction packet to the predesignated parity.

Parity for instruction packets

Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

Using the least significant bits of a called function's address to switch processor modes

A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

Selective translation lookaside buffer search and page fault

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Austin, TX, United States of America

Erich Plondke