Cadence Design Systems, Inc.

Erich Marschner

Alok Jain

Manu Chopra

Swapnajit Chakraborti

Verification model of static state retention behavior of a state saving element design during power shut off of the state saving element in an integrated circuit design including: creating in a computer readable medium a model of a single edge triggered state saving element; and creating in the computer readable medium clock gate logic that suspends saving of new states by the single state saving element upon the occurrence of a first state retention signal in preparation for power shut off.

State retention for formal verification

A mechanism is disclosed for recognizing and functionally abstracting a column of memory cells. According to one embodiment, a column of n (where n is an integer greater than 1) memory cells is identified in a description of a circuit. One of the n memory cells is selected as a representative memory cell. Then, the column of n memory cells is represented as a single-memory-cell column comprising the representative memory cell. The column is thereafter functionally abstracted to derive a logic-level representation of the memory cell. After that is done, n&#x2212;1 additional instances of the logic-level representation are generated. In this manner, the column of n memory cells is functionally abstracted as a column of n logic-level representations of the representative memory cell.

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Ellicott City, MD, United States of America

Erich Marschner