Exel Microelectronics, Inc.

Other

Erich Goetting

Yun Hwang

A programmable logic array which can produce single level logic or can produce multiple level logic through the use of internal feedback loops. A plurality of input lines intersect a plurality of term lines and can be programmable coupled to the term lines. A number of term lines provide a feedback input which intersects all of the term lines and can be programmably coupled to the tem lines. Teh input lines and the feedback input lines form a single matrix with the term lines.

Single function programmable logic array circuit

An improved field programmable matrix circuit. The matrix circuit includes a plurality of pairs of input lines having noninverted and inverted inputs. These input lines intersect a plurality of output column lines. A single transistor is used to provide a programmable connection to each column line from both the inverted and noninverted inputs of an input line pair. The transistor has a source, a drain and a gate with either the source or the drain coupled to a voltage potential and the other of the source or the drain coupled to an output column line. The gate is alternately coupled to a noninverted input, an inverted output, or a second voltage potential. The second voltage potential is coupled when it is desired to hold the transistor in an off state.

Field programmable matrix circuit for EEPROM logic cells

An improved security circuit for a programmable logic array. One of the programmable elements of the array is designated as a security element, and its output is coupled to a latching mechanism. The output of the latching mechanism is coupled to a mechanism for disabling the read output of the array. The latching mechanism is enabled for a short time by a pulse when power is applied to the circuit. Thus, when power is first applied, the security fuse has not been set and the latch output will allow data to be read. While power is applied, all of the programmable elements can be set, including the security element. All the elements, including the security fuse, can then be verified by reading them out. When power is turned off and subsequently reapplied, the latch will then be enabled and the set security fuse level will appear at the latch output, thereby disabling the reading out of the program data. The present invention thus allows verification of the setting of the security fuse and verification of the other programmable elements after the security fuse has been set.

Security element circuit for programmable logic array

An improved architecture for programming an output cell (macro cell) in a PLD. The memory cells for the macro cell are stored in the main array itself. Upon power-up, a power-on sense circuit senses the presence of power and enables an architecture portion of the main array while disabling the rest of the main array. The power-on sense signal also enables a path from the output of the array to the macro cell elements to be programmed. When the power-on sense signal is removed a short time after power-up, this path is blocked so that the array outputs continue on their normal path and the architecture portion of the array is disabled while the rest of the array is enabled for normal operation.

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Cupertino, CA, United States of America

Erich Goetting