International Business Machines Corporation

Erich C Schanzenbach

Scott Whitney Gould

Howard Harold Smith

Raju Balasubramanian

Anurag P Umbarkar

Andrew D Huber

Patrick M Ryan

Bing Chen

Mark Kwang-Jen Hsu

Steven H Voldman

Joseph N Kozhaya

Douglas Willard Stout

Paul Steven Zuchowski

Ivan L Wemple

Patrick H Buffet

Ciaran J Brennan

William John Livingstone

Jeannie H Panner

Paul E Dunn

Robert A Proctor

Rafik R Habra

Debra K Korejwa

Philip S Homsinger

Paul D Montane

Lin Lin

A method and system for implementing automated identification of optimal sense point (SP) and sector locations in various on-chip linear voltage regulator designs. A customized cost function is used along with predefined performance metrics to identify optimal SP and sector locations, under user-defined design constraints. The SP and sector locations are updated based on the identified optimization results, and the updated SP and sector locations are applied to an on-chip linear voltage regulator design to provide enhanced regulator performance and to ensure proper operation.

Implementing automated identification of optimal sense point and sector locations in various on-chip linear voltage regulator designs

A linear circuit simulator can be supplied with a linear power distribution model of an integrated circuit (IC) and two sets of voltage regulator equivalent resistances. The linear circuit simulator can then be used to calculate two voltages, at a sense point of the IC, corresponding to the two sets of voltage regulator equivalent resistances. The two sets of voltage regulator equivalent resistances and the two voltages at the IC sense point can be used to interpolate a slope of a resistance versus voltage curve of the linear power distribution model. The slope can be used to calculate an updated set of voltage regulator equivalent resistances, which can be used by the linear circuit simulator to calculate a set of performance metrics and an updated voltage at the sense point of the IC.

Evaluating on-chip voltage regulation

An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.

Electrostatic discharge failure avoidance through interaction between floorplanning and power routing

A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N&#x2212;1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.

Method and apparatus for performing power routing on a voltage island within an integrated circuit chip

A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levelsto N&#x2212;1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.

A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.

Method of automated design and checking for ESD robustness

A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.

Method of analyzing integrated circuit power distribution in chips containing voltage islands

In any of the post-global physical design phases an integrated circuit chip is wired in parallel. The chip is first divided into adjacent bays with rough wiring coordinates from the global wiring phase. Next the bays are grouped into bay groups, with each bay group containing a contiguous group of non-edge bays as well as edge bays which are adjacent another bay group. Each bay group is assigned to a wiring task on a processor, so that the wiring of the bay groups is performed in parallel, using the rough coordinates from the global wiring phase. The wiring tasks are coordinated regarding edge bays in order to achieve wiring consistency between bay groups.

Parallel approach to chip wiring

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Dover Plains, NY, United States of America

Erich C Schanzenbach