Advanced Micro Devices Corporation

Intel Corporation

Globalfoundries Inc.

Null Networks LLC

Erich Boleyn

Gilbert A Neiger

Richard A Uhlig

Mark Douglas Hummel

Andrew Gregory Kegel

Keith Lowery

Michael A Kozuch

Thomas R Woller

Patryk Kaminski

Andrew F Glew

Benjamin Charles Serebrin

Erik C Cota-Robles

Dion Rodgers

Stalinselvaraj Jeyasingh

Lawrence O Smith

Alain Kagi

Larry O Smith

Andy Glew

Alfred C She

Jonathan A Tuchow

Steve M Bennett

Qiyong B Bian

Zhi Wang

Juliet Z Cai

Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system.

Hypervisor isolation of processor cores to enable computing accelerator cores

An API including a registration function and a configuration function, is provided to an optical networking apparatus to facilitate registration of configuration specification delimiter pairs by service routines of function blocks of multi-protocol optical networking modules (MPONM), and extraction of configuration specifications for the function blocks from a configuration specification input set using the registered configuration specification delimiter pairs. In one embodiment, the configuration function also receives current configuration of the function blocks, and merges the received current configurations of the function blocks into a configuration specification output set, separating the merged configuration specification using the registered configuration specification delimiters.

Extensible configuration methods for optical networking apparatuses with multiple multi-protocol optical networking modules

Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.

Systems and methods implementing non-shared page tables for sharing memory resources managed by a main operating system with accelerator devices

Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).

IOMMU architected TLB support

In an embodiment, a system memory stores a set of input/output (I/O) translation tables. One or more I/O devices initiate direct memory access (DMA) requests including virtual addresses. An I/O memory management unit (IOMMU) is coupled to the I/O devices and the system memory, wherein the IOMMU is configured to translate the virtual addresses in the DMA requests to physical addresses to access the system memory according to an I/O translation mechanism implemented by the IOMMU. The IOMMU comprises one or more caches, and is configured to read translation data from the I/O translation tables responsive to a prefetch command that specifies a first virtual address. The reads are responsive to the first virtual address and the I/O translation mechanism, and the IOMMU is configured to store data in the caches responsive to the read translation data.

Translation data prefetch in an IOMMU

Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.

Methods and systems to control virtual machines

A method and an apparatus are used to efficiently translate memory addresses. The translation scheme yields a translated address, a memory type for the translated address, and a fault bit for the translation.

Method and apparatus for translating guest physical addresses in a virtual machine environment

Growing community of inventors

Portland, OR, United States of America

Erich Boleyn