Vixs Systems, Inc.

Eric Young

Edward Hong

Indra Laksono

Dong Liu

Kai Yang

Hongri Wang

Xu Gang Zhao

Chun-Chin David Yeh

Xu Gang (Wilf) Zhao

Xin Guo

Wendy Wai Yin Cheung

Qi Yang

A video device includes a codec engine to process video data to generate a stream of pixel blocks representing a picture of a sequence of pictures represented by the video data, an image processing module to receive the stream of pixel blocks via a local path between the codec engine and the image processing module and to perform at least one image processing function for the picture using pixel blocks of the stream of pixel blocks received via the local path to generate image processing result data representative of the picture. The video device further includes a storage interface coupleable to a storage component, the storage interface to provide the image processing result data for storage at the storage component.

Codec engine with inline image processing

A scaled motion search section can be used in a video processing device that processes a video input signal that includes a plurality of pictures. The scaled motion search section includes a downscaling module that downscales the plurality of pictures to generate a plurality of downscaled pictures. A reduced-scale motion search module generates a plurality of motion vector candidates at a downscaled resolution, based on the plurality of downscaled pictures. The reduced-scale motion search module includes a column buffer that stores a column of reference data and generates the plurality of motion vector candidates based on a parallel processing of the column of reference data for a group of adjacent macroblock pairs.

Scaled motion search section with parallel processing and method for use therewith

A video processing device includes a video processing unit that decodes a video input signal into a decoded video signal in accordance with a video compression protocol, based on uncompressed video frame data. A tile engine includes a tile accumulation module that accumulates the uncompressed video frame data into a plurality of tile units, wherein each of the plurality of tile units includes a plurality of video span units. A tile compression/decompression module generates compressed video frame data for storage in a compressed video frame buffer by compressing the plurality of video span units into a plurality of compressed video span units and further that retrieves the compressed video frame data from the compressed video frame buffer by retrieving the plurality of compressed video span units and generating the uncompressed video frame data by decompressing the plurality of compressed video span units.

Video processor with reduced memory bandwidth and methods for use therewith

A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

Multi-format video decoder with vector processing instructions and methods for use therewith

A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units includes at least one filter vector processor that operates in conjunction with a plurality of programmable filter parameters.

Multi-format video decoder with filter vector processing and methods for use therewith

A video processing device operates in an encoding mode when a mode selection signal has a first value and operates in a decoding mode when the mode selection signal has a second value. The encoding mode utilizes a plurality of function specific hardware engines that each perform a specific coding function and the decoding module utilizes at least one of the plurality of hardware engines.

Video processing system and device with encoding and decoding modes and method for use therewith

A technique for encoding and decoding video information uses a plurality of video processing modules (VPMs), whereby each video processing module is dedicated to a particular video processing function, such as filtering, matrix arithmetic operations, and the like. Information is transferred between the video processing modules using a set of first-in first-out (FIFO) buffers. For example, to transfer pixel information from a first VPM to a second VPM, the first VPM stores the pixel information at the head of a FIFO buffer, while the second VPM retrieves information from the tail of the FIFO buffer. The FIFO buffer thus permits transfer of information between the VPMs without storage of the information to a cache or other techniques that can reduce video processing speed.

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Markham, Canada

Eric Young