Cypress Semiconductor Corporation

Eric Wolf Gross

Cathal G Phelan

Stefan-Cristian Rezeanu

James D Allan

Vijay Srinivasaraghavan

Emad Hamadeh

Robert W Manning

An impedance matching circuit has a number of buffers each having a variable impedance circuit. A variable impedance sense control block has an impedance code as an output. A sequencing circuit couples the impedance code of the variable impedance sense control block to the variable impedance circuit of each of the buffers.

Impedance matching circuit and method

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports

An adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the signal propagation speed as noise conditions worsen. This active filter has a level shifting inverter, which inverts the input signal and converts the logic levels of the input signal into chip logic levels. This inverted input signal is presented at the input of a driver inverter, which once again inverts the signal. This second inversion filters out input noise, because a voltage controlled device (which is attached to the driver inverter) reduces the switching speed of this inverter as the noise condition worsen; this reduction in switching speed reduces the propagation speed and thus filters out noise. In addition, two cascaded voltage generator circuits create a reference voltage generator, that enables the voltage controlled device to detect changes in noise conditions, by providing it with a reference voltage that varies in a controlled and specific manner with the changes in transistor conductance parameters, power supply voltages, and operating temperatures. This reference voltage generator controls the variance of the reference voltage in two manners. First, this generator utilizes a positive temperature coefficient floating voltage source to increase (in a controlled fashion) the variance of the reference voltage with changes in the temperature. Second, this generator uses a feedback path, between the first and the second voltage generator circuits, to compensate for uncontrolled variations of the reference voltage due to process variations in transistor conductance parameters.

Active filtering method and apparatus

A differential latch sense amplifier for memories has (a) a first differential input circuit for detecting and shifting the voltage levels of the first and second input signals and coupled to first and second sense nodes, (b) a cross-coupled latch for providing gain to the first and second sense nodes, (c) a precharge circuit for precharging and equalizing the first and second sense nodes, (d) a first tristatable output driver for providing a first feedback, for outputting the voltage of the first sense node to a first output node, and for receiving data, (e) a second tristatable output driver for providing a second feedback, for outputting the voltage of the second sense node to a second output node, and for receiving data, and (f) a first feedback circuit for increasing the voltage gain and decreasing the sense output response time at the first and second sense nodes and for being controlled by the first and second tristatable output drivers. The feedback circuit is coupled to the first and second tristatable output drivers in such a way that the feedback circuit is disabled during a standby period or between read or write cycles. To minimize layout area, the differential latch sense amplifier may further include a second differential input circuit and a second feedback circuit sharing the cross-coupled latch and precharge circuits. To write data into the memory cells, the differential latch sense amplifier has data transfer pass gates controlled by a west write circuit and an east write circuit.

Growing community of inventors

Mountain View, CA, United States of America

Eric Wolf Gross