International Business Machines Corporation

Marvell Asia Pte., Ltd.

Globalfoundries Inc.

Eric W Tremble

Wolfgang Sauter

Mark William Kuemerle

Timothy W Budell

David Brian Stone

Anson Jay Call

Charles S Chiu

Erwin B Cohen

Dany Minier

Nicholas A Polomoff

Ivan L Wemple

David C Reynolds

Kurt A Carlsen

Umberto Garofano

Seungman Choi

Brian P Welch

Ze Gui Pang

Eric S Parent

Haitian Hu

David Toub

Aatreya Chakravarti

Samer Michael Akiki

Christoph Sauter

Jawahar P Nayak

Daniel P Greenberg

A system for designing placement locations for Input/Output (I/O) blocks in an electronic device is disclosed. The system includes an interface and a processor. The interface is configured to receive a requirement that specifies at least multiple I/O blocks to be laid-out along a periphery of an electronic device that implements a network communication device. The processor is configured to generate a plurality of candidate layouts for the electronic device, the candidate layouts differing from one another at least in an arrangement of the specified I/O blocks along the periphery, to estimate respective costs associated with at least some of the candidate layouts, and to present at least some of the candidate layouts and the respective estimated costs to a user.

Quick floorplanning tool

An electronic network device includes: (i) an integrated circuit (IC) die configured to exchange signals between the electronic network device and one or more other devices that are remote from the electronic network device, (ii) a plurality of transceiver dies, separate from the IC die, the plurality of transceiver dies being disposed along at least a first axis extending at an acute angle from an edge of the IC die and intersecting the edge at a first point, the transceiver dies being configured to exchange the signals between the IC die and the other devices, and (iii) electrical connections configured to connect between the IC die and at least one of the transceiver dies for exchanging at least some of the signals between the IC die and the transceiver dies.

Lateral escape using triangular structure of transceivers

The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.

Partitioned substrates with interconnect bridge

An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Interconnected integrated circuit (IC) chip structure and packaging and method of forming same

A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.

Split ball grid array pad for multi-chip modules

The present disclosure relates to interface structures and, more particularly, to integrated interface structures with both parallel and serial interfaces and methods of manufacture. The integrated interface structure includes: a substrate; a plurality of serial interface connections integrated on the substrate; and a plurality of parallel interface connections on the integrated substrate and within spaces between sets of the plurality of serial interface connections.

Integrated interface structure

A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.

Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.

Early decoupling capacitor optimization method for hierarchical circuit design

In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit.

System-level method for reducing power supply noise in an electronic system

A method for modeling bond wires in an IC package for predicting noise effects generated by electromagnetic coupling in complex bond wire configurations. A look-up table of equivalent LC circuit models for the bond wires is generated that accurately predicts the effects of the bond wire circuitry of a signal transmission system. Switch and mirror techniques are applied to reduce the bond wire configurations necessary to simulate. The method includes: setting parameters related to the IC package layout of groups of bond wires; sub-dividing each group of bond wires into regions, each including a portion of the bond wire or its corresponding pad, and generating dissection planes for the regions consisting of the bond wires; performing a 3D simulation on the regions consisting of the corresponding pads, and a 2D simulation for each dissection plane; constructing equivalent circuit models for groups of bond wires and corresponding pads based on the 3D and 2D simulations results; inputting the equivalent circuit models into a circuit simulator to measure the noise effects; and modifying the layout geometry to meet noise targets.

Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages

After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time.

Automatic verification of adequate conductive return-current paths

The present invention provides a redistribution package having an upper surface that includes contacts with reduced pitch that correspond, for example, to that of a Controlled Collapse Chip Connection ('C4') structure formed on a chip, and a lower surface having contacts with increased pitch that correspond, for example, to a printed circuit board employing ball grid array ('BGA') pads. A series of power, signal and ground conductors extend through the body of the redistribution package and interconnect the circuit board contacts to the chip contacts.

Growing community of inventors

Jericho, VT, United States of America

Eric W Tremble