Dell USA L P

Advanced Micro Devices Corporation

Eric W Schieve

Richard W Finch

Gary W Abbott

Charles P Zeller

Wai-Ming Richard Chan

Joseph A Vivio

Methods for debugging a processor based on executing a randomly created and randomly executed executable on a fabricated processor. The executable may execute via startup firmware. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. The processor Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Method of debugging a processor

Methods for designing a processor based on executing a randomly created and randomly executed executable on a fabricated processor. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Disclosed are a system and method for providing fault isolation in a computer system including a central processing unit (&ldquo;CPU&rdquo;) capable of issuing a signal to a memory to retrieve a requested instruction from the memory when the CPU is booted. The disclosed invention comprises an interception and substitution circuit, coupled to the CPU, capable of intercepting the signal and providing an alternative diagnostics instruction to the CPU in lieu of the requested instruction, the alternative diagnostics instruction providing an indication of proper functioning of the computer system when executed by the CPU. The circuit allows a user to determine whether the CPU and components proximate the CPU are functioning, even when a fault renders conventional, embedded power-on self-test routines non-functional.

Computer system having an instruction interception and substitution circuit

A read/writable memory formed in the same semiconductor chip as a microprocessor is employed in testing a plurality of hardware interrupt service routines initiated by corresponding devices (and components of devices) during a power-on, self-test(POST) of a computer system. The POST is set in the read-only memory(ROM) of the computer system. The read/writable memory, which is ordinarily inoperative during the POST, is used for storing a diagnostic interrupt vector table, which has a list of interrupt numbers and corresponding addresses of the respective interrupt routines. This table is normally subject to change because each device and each of its components have different interrupt service routines, requiring different addresses for the same interrupt number. The random access memory(RAM) has not yet been tested in the POST, and is not regarded as reliable for the hardware interrupt testing and therefore the read/writable memory is used for such testing.

Method and apparatus for testing hardware interrupt service routines in

The invention relates to a method for rotating a source pixel matrix to provide a rotated destination matrix. The method operates on a computer system which includes a processor, a memory and a temporary storage portion. The temporary storage portion includes a plurality of rows where each row includes a plurality of storage locations. The method includes the steps of loading a first set of rows of the temporary storage portion with a lower portion of the source pixel matrix, loading a second set of rows of the temporary storage portion with an upper portion of the source pixel matrix, skewing the source pixel matrix loaded in first and second sets of rows to provide a skewed pixel matrix, alternately rotating selected portions of the skewed pixel matrix stored in selected rows of the first and second sets of rows horizontally and vertically to provide a rotated pixel matrix, and unscrambling the rotated pixel matrix to provide the rotated destination matrix.

System for performing rotation of pixel matrices

Disclosed are a system and method for loading diagnostic routines for execution in a computer system. The method comprises the steps of (1) executing a boot loading routine stored in non-volatile memory within the computer system, the boot loading routine providing an environment in lieu of an operating system of the computer system within which to execute diagnostic routines, the boot loading routine including a decompression routine, (2) decompressing a compressed diagnostic routine stored in the non-volatile memory into video random access memory (RAM) and (3) executing the decompressed diagnostic routine under control of the boot loading routine. The present invention, in its preferred embodiment, allows relatively large diagnostic routines to be stored in electrically erasable programmable read only memory ('EEPROM') and decompressed, as required, into video RAM for execution, without requiring the computer's operating system to function.

System and method for loading compressed embedded diagnostics

A watchdog timer circuit of the present invention monitors a computer system (S) during diagnostic testing and resets the system when it is nonfunctioning. A real-time clock (RTC) (21), programmed by a central processing unit (CPU) (29) to run for a period of time, produces a reset signal after the period of time elapses. Typically this time period relates to a diagnostic program being run. The reset signal serves as an input to reset circuitry (28) which immediately transmits a nonmaskable interrupt (NMI) to the CPU (29) and, after a delay period, transmits a hardware reset signal to the CPU (29). When functioning properly, the CPU (29) prepares for the hardware reset signal that is produced by the reset circuitry (28) and avoids being reset by the hardware reset signal. However, when the CPU (29) is not functioning properly, the hardware reset signal resets the CPU (29). Additional circuitry stores information regarding where the system (S) failed during the diagnostic testing and retrieves such information for the user upon reset. An additional feature resets all of the components within the system (S) upon a CPU (29) reset via power reset circuitry.

Watchdog timer for computer system reset

Disclosed are a circuit and method for dynamically determining cache memory size. The method comprises the steps of (1) writing a replacement data pattern into a first addressable location of a cacheable portion of addressable space, thereby placing the replacement data pattern into a corresponding first addressable location in a cache memory and setting a tag in the first addressable location, (2) accessing an assumed number of remaining addressable locations in the portion of the addressable space thereby setting tags in each of the remaining addressable locations and (3) reading the first addressable location in the cache memory to determine whether the replacement data pattern remains in the first addressable location, the cache memory being of an assumed size if the replacement data pattern is not in the first addressable location in the cache memory. The circuit and method are able to size cache memory without reference to cache size data stored in cache controllers or hardware timers.

Method and circuit for determining the size of a cache memory

A memory write disable circuit which disables write operations to main memory during cache diagnostics and thus provides a generic means for testing cache memory systems. Disabling write operations to main memory allows the diagnostics to easily distinguish between cache hits and cache misses during diagnostics. The disable circuit operates by disabling the output enable for the main memory write signal. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.

Cache testability circuit for embedded diagnostics

Disclosed are a system and method for loading diagnostic routines images from disk for execution in a computer system. The method comprises the steps of (1) executing a boot loading routine stored in non-volatile memory within the computer system, the boot loading routine providing an environment in lieu of an operating system of the computer system within which to execute diagnostic routines, the boot loading routine including a disk access routine, (2) retrieving a diagnostic routine stored as an image on a disk into video random access memory ('RAM') with the disk access routine and (3) executing the retrieved diagnostic routine under control of the boot loading routine. The present invention, in its preferred embodiment, allows relatively large diagnostic routines to be stored in the form of images on a disk drive in the computer system and retrieved, as required, into video RAM for execution, without requiring the computer's operating system to function.

System and method for loading diagnostics routines from disk

Disclosed are a circuit and method for remote diagnosis of personal computers. The method comprises the steps of (1) confirming an existence and a proper operation of a modem coupled to the personal computer, the step of confirming performed in a central processing unit ('CPU') of the personal computer and in a diagnostic environment independent of a normal operating system of the personal computer, (2) receiving an indication of a selection of diagnostic routines to be performed from a remote location via the modem and (3) performing selected ones of the diagnostic routines as a function of the selection. The present invention allows an experienced technician located remotely from the computer to interact as though seated in front of it, to thereby allow remote diagnosis of even critical faults that prevent the computer from booting.

Circuit and method for remote diagnosis of personal computers

Disclosed are an apparatus and method for testing a direct memory access ('DMA') controller. The apparatus comprises (1) a virtual control device including a virtual control latch, the virtual control device coupled to a request input of the DMA controller and capable of transmitting a signal to the DMA controller representing a request to transfer data and (2) a virtual input/output ('I/O') device including a virtual I/O latch, an acknowledgement output of the DMA controller coupled to the virtual I/O device, the virtual I/O latch capable of storing the data for use by the DMA controller. In its preferred embodiment, the present invention operates within the confines of IBM-compatible personal computer architecture, allowing DMA controller functionality to be tested directly.

Circuit and method for testing direct memory access circuitry

Disclosed is a diagnostic procedure for identifying and sizing computer memory, which, in the preferred embodiment of the invention, comprises SIMMs. The procedure comprises the steps of (1) testing a plurality of memory locations in the unit by writing and reading bit patterns to memory locations in succession to determine whether any of the memory locations contains any responding bits and (2) stipulating the unit to be present when a number of the memory locations having any responding bits reaches a predetermined minimum number. The procedure is uniquely designed to detect memory which is not fully functional.

Diagnostic procedure for identifying presence of computer memory

Disclosed are a system and method for providing user-invocable, non disk-based diagnostics routines for a personal computer. The method comprises the steps of (1) storing a diagnostics routine capable of performing diagnostic tests on portions of the personal computer in ROM, (2) monitoring a status of a reset button coupled to the personal computer and (3) executing the diagnostics routine if the reset button is pressed twice within a preselected period of time. The disclosed system and method allow a user to control the invocation of a diagnostics routine that needs a minimum of functioning computer hardware to execute.

Personal computer employing reset button to enter ROM-based diagnostics

A computer which carries its BIOS in a Flash EPROM. A UV-EPROM carries a redundant BIOS, which can be overlaid onto the BIOS address space by selection with a physical switch. The BIOS contains a small core software program, at the BIOS entry point, which checks BIOS integrity, and provides for reloading the Flash EPROM's BIOS if needed (from a floppy disk, or by copying the entire contents of the UV-EPROM).

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Austin, TX, United States of America

Eric W Schieve