Qualcomm Incorporated

Advanced Micro Devices Corporation

Intel Corporation

Oracle International Corporation

Other

Eric W Mahurin

Elmoustapha Ould-Ahmed-Vall

Vinodh Gopal

Bret L Toll

Martin Guy Dixon

Sean Mirkes

Maxim Loktyukhin

David L Kreitzer

Erich Plondke

David J Hoyle

Vijay Kiran Kalyanam

Albert Danysh

Lucian Codrescu

Yuan C Chou

Suresh Kumar Venkumahanti

Michael T Clark

Rexford Alan Hill

Hitesh Kumar Gupta

Ahmad Mahmoud Radaideh

Jakub Pawel Golab

Scott A White

Colin Beaton Verrilli

Dexter Tamio Chun

Roger A Golliver

Rahul Gulati

Brian D McMinn

Christopher E Koob

Ajay Anant Ingle

Martin Saint-Laurent

Sridhar Samudrala

Jeffrey E Trull

Aaron Douglass Lamb

Tijmen Pieter Frederik Blankevoort

Robert C Burd

Jeff Wiedemeier

Sanjay Bhagawan Patil

Mohammad Reza Kakoee

Markus Nagel

Marinus Willem Van Baalen

Robert C Thaden

Dimitry Patent

Jeffrey A Correll

Steven C Hesley

Jeffery E Short

Andrey Kuzmin

Andrii Skliar

Diego Andres Guerra

Butchi Venkata Chaitanya Akondi

Brian Kahne

Christopher B Ang

A processor-implemented method includes bit shifting a binary representation of a neural network parameter. The neural network parameter has fewer bits, b, than a number of hardware bits, B, supported by hardware that processes the neural network parameter. The bit shifting effectively multiplies the neural network parameter by 2. The method also includes dividing a quantization scale by 2to obtain an updated quantization scale. The method further includes quantizing the bit shifted binary representation with the updated quantization scale to obtain a value for the neural network parameter.

Simulated low bit-width quantization using bit shifted neural network parameters

An aspect of the disclosure relates to a data processing system, including: an input medium configured to include a first set of blocks of data including a first set of block of compressed data and a first set of metadata, respectively; an output medium configured to include a first set of blocks of decompressed data each having a predetermined number of decompressed elements; and a set of single instruction multiple data (SIMD) processors configured to: access the first set of blocks of data from the input medium, respectively; decompress the first set of blocks of compressed data to generate the first set of blocks of decompressed data based on the first set of metadata, respectively; and provide the first set of blocks of decompressed data to the output medium, respectively.

Single instruction multiple data (SIMD) sparse decompression with variable density

Certain aspects of the present disclosure provide techniques and apparatus for hardware-based floating point exponent extraction. Aspects include invoking an instruction in an instruction set architecture (ISA) associated with the one or more processors in order to extract an exponent from a floating point value. Aspects include, in response to the invoking, executing machine code of the instruction using the one or more processors to compute a floor of a base two logarithm of the floating point value to determine the exponent. Aspects include performing one or more actions using the exponent.

Processor instruction for dynamic floating point exponent extraction

A device includes one or more processors configured to retrieve a first block of data, the data corresponding to array of values arranged along at least a first dimension and a second dimension, to retrieve at least a portion of a second block of the data, and to perform a first hybrid convolution operation that applies a filter across the first block and at least the portion of the second block to generate output data. The output data includes a first accumulated block and at least a portion of a second accumulated block. The one or more processors are also configured to store the first accumulated block as first output data. The portion of the second block is adjacent to the first block along the first dimension and the portion of the second accumulated block is adjacent to the first accumulated block along the second dimension.

Hybrid convolution operation

A method of constraining data represented in a deep neural network is described. The method includes determining an initial shifting specified to convert a fixed-point input value to a floating-point output value. The method also includes determining an additional shifting specified to constrain a dynamic range during converting of the fixed-point input value to the floating-point output value. The method further includes performing both the initial shifting and the additional shifting together to form a dynamic, range constrained, normalized floating-point output value.

Constraining function approximation hardware integrated with fixed-point to floating-point conversion

A device includes a scoreboard and a processor. The scoreboard includes scoreboard entries configured to store information regarding one or more uncompleted memory access operations. The scoreboard also includes a dependency matrix configured to store dependency information corresponding to the scoreboard entries. The processor is configured to retrieve a first memory access instruction that indicates a first address range of a first memory access operation, and to add an indication of the first memory access instruction to a first scoreboard entry. The processor is further configured to, based on determining that the first address range at least partially overlaps a second address range associated with a second scoreboard entry that corresponds to a second memory access instruction, set an element of the dependency matrix to have a has-dependency value indicating a dependency of the first scoreboard entry on the second scoreboard entry.

Memory access management

Inserting a proxy read instruction in an instruction pipeline in a processor is disclosed. A scheduler circuit is configured to recognize when a produced value generated by execution of a producer instruction in the instruction pipeline will not be available through a data forwarding path to be consumed for processing of a subsequent consumer instruction. In this case, the scheduling circuit is configured to insert a proxy read instruction in the instruction pipeline to cause execution of an operation to generate the same produced value as was generated by previous execution of producer instruction in the instruction pipeline. Thus, the produced value will remain available in the instruction pipeline to again be available through a data forwarding path to an earlier stage of the instruction pipeline to be consumed by a consumer instruction, which may avoid a pipeline stall.

Inserting a proxy read instruction in an instruction pipeline in a processor

Systems and methods for power control based on performance modification through pulse modulation include an integrated circuit (IC) that may evaluate certain limit conditions within a computing device and compare the limit conditions to corresponding predefined thresholds. When a given predefined threshold is exceeded, an overage signal may be sent to a limits management circuit within the initial IC or another IC. The limits management circuit may generate a single-bit throttle signal through a pulse modulation circuit. The single-bit throttle signal may modify internal processing of an associated processor, which in turn changes power consumption.

Power control based on performance modification through pulse modulation

A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW based microprocessor architecture may include a temporary cache for use in writing/reading a temporary memory value during a single VLIW packet cycle. The temporary cache is different from the normal register bank that does not allow writing and then reading the value just written during the same VLIW packet cycle.

System, apparatus, and method for a transient load instruction within a VLIW operation

A processor includes a vector register configured to load data responsive to a special purpose load instruction. The processor also includes circuitry configured to replicate a selected sub-vector value from the vector register.

System and method of loading and replication of sub-vector values

Systems and methods for multi-thread power limiting via a shared limit estimates power consumed in a processing core on a thread-by-thread basis by counting how many power events occur in each thread. Power consumed by each thread is approximated based on the number of power events that have occurred. Power consumed by individual threads is compared to a shared power limit derived from a sum of the power consumed by all threads. Threads that are above the shared power limit are stalled while threads below the shared power limit are allowed to continue without throttling. In this fashion, the most power intensive threads are throttled to stay below the shared power limit while still maintaining performance.

Multi-thread power limiting via shared limit

A clock gating system (CGS) includes a digital power estimator configured to generate indications of a predicted energy consumption per cycle of a clock signal and a maximum energy consumption per cycle of the clock signal. The CGS further includes a voltage-clock gate (VCG) circuit coupled to the digital power estimator. The VCG circuit is configured to gate and un-gate the clock signal based on the indications prior to occurrence of a voltage droop event and using hardware voltage model circuitry of the VCG circuit. The VCG circuit is further configured to gate the clock signal based on an undershoot phase associated with the voltage droop event and to un-gate the clock signal based on an overshoot phase associated with the voltage droop event.

Proactive clock gating system to mitigate supply voltage droops

Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

Processor to perform a bit range isolation instruction

A system and a method for error-correction code ('ECC') error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.

System and method for online functional testing for error-correcting code function

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Austin, TX, United States of America

Eric W Mahurin