Texas Instruments Corporation

Eric W Beach

Philipp Steinmann

Walter Baker Meinel

Vladimir Frank Drobny

Derek W Robinson

Rajneesh Jaiswal

Abbas Ali

Siang Ping Kwok

Brian L Vialpando

Eric L Hoyt

Pinghai Hao

Weidong Tian

Jimmy R Naylor

Tony Thanh Phan

Pushpa Mahalingam

Martin B Mollat

Kyle Mitchell Flessner

Robert Hung Nguyen

Connie Wang

Barbara M Barnes

Karen Elizabeth Burks

Michelle R Keramidas

Arthur Pan

MrPushpa Mahalingam

An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Metal thin film resistor and process

An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor. A fifth interconnect conductor extends through an opening in the first dielectric layer to contact a circuit element.

Thin film resistors integrated at two different metal single die

A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.

Method to manufacture a thin film resistor

An integrated circuit back end capacitor structure includes a first dielectric layer on a substrate, a thin film bottom plate on the first dielectric layer, and a second dielectric layer on the first dielectric layer and the bottom plate, and a thin film top plate disposed on the second dielectric layer. The thin film top plate and bottom plate are composed of thin film resistive layers, such as sichrome, which also are utilized to form back end thin film resistors having various properties. Interconnect conductors of a metallization layer contact the top and bottom plates through corresponding vias.

Back end thin film capacitor having plates at thin film resistor and first metallization layer levels

An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer () formed on a semiconductor substrate (), a first thin film resistor () disposed on the first oxide layer (), and a second oxide layer () disposed over the first oxide layer () and first thin film resistor (). A second thin film resistor () is formed on the second oxide layer () and a third oxide layer () is formed over the second thin film resistor () and the second oxide layer (). Interconnect metallization elements (A,B &A,B) disposed on at least one of the second () and third () oxide layers electrically contact the circuit element (), terminals of the first thin film resistor (), and terminals of the second thin film resistor (), respectively, through corresponding contact openings through at least one of the second () and third () oxide layers.

Integration of thin film resistors having different TCRs into single die

Back end thin film capacitor having both plates of thin film resistor material at single metallization layer

A method of determining the degree of calibration of an RTP chamber () includes providing a test wafer having a deposited sichrome layer () of sheet resistance Rsi on an oxide layer () formed on a silicon substrate (). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change &#x394;Rs=Rsi&#x2212;Rsf is computed. The 'actual' value of the anneal temperature is determined from predetermined characterizing information relating &#x394;Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of &#x394;Rs if the difference between the 'actual' value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error. The basic technique can be utilized to determine an anneal time and anneal duration for annealing sichrome resistors to precisely adjust the sheet resistance or TCR thereof.

Rapid thermal anneal equipment and method using sichrome film

A thin film resistor structure includes a plurality of thin film resistor sections. Conductive vias () are disposed on a first end of each of the thin film resistor sections, respectively. The first conductor () is connected to the vias of the first end, and a second conductor () is connected to vias on a second end of each of the thin film resistor sections. A distribution of a parameter of a batch of circuits including the thin film resistor structure indicates a systematic error in resistance values. Based on analysis of the distribution and the circuit, or more of the vias are individually moved at the layout grid level by a layout grid address unit to reduce the systematic error by making corresponding adjustments on a via reticle of a mask set used for making the circuits. Expensive laser trimming of thin film resistors of the circuit is thereby avoided.

Nonlinear via arrays for resistors to reduce systematic circuit offsets

Thin film resistors integrated at two different metal interconnect levels of single die

An integrated circuit thin film resistor structure includes a first dielectric layer (A) disposed on a semiconductor layer (), a first dummy fill layer (A) disposed on the first dielectric layer (B), a second dielectric layer (C) disposed on the first dummy fill layer (A), the second dielectric layer (B) having a first planar surface (-), a first thin film resistor () disposed on the first planar surface (-) over the first dummy fill layer (A). A first metal interconnect layer (A,B) includes a first portion (A) contacting a first head portion of the thin film resistor (). A third dielectric layer () is disposed on the thin film resistor () and the first metal interconnect layer (A,B). Preferably, the first thin film resistor () is symmetrically aligned with the first dummy fill layer (A). In the described embodiments, the first dummy fill layer is composed of metal (integrated circuit metallization).

Thin film resistor and dummy fill structure and method to improve stability and reduce self-heating

A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.

Thin film resistor structure and method of fabricating a thin film resistor structure

A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.

Thin film resistor integration in a dual damascene structure

A method of making integrated circuit thin film resistor includes forming a first dielectric layer (B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (A) on the first dielectric layer, and forming a second dielectric layer (D) over the first dummy fill layer. A thin film resistor () is formed on the second dielectric layer (D). A first inter-level dielectric layer (A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (). Preferably, the first dummy fill layer is formed so as to extend sufficiently far beyond ends of the thin-film resistor to ensure only a negligible amount of systematic resistance error due to misalignment.

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Tuscon, AZ, United States of America

Eric W Beach